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p r o du c t o v e r vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy dual, 14 - bit, 1.25 gsps, 1.2 v/2.5 v, analog - to - digital converter data sheet ad9680 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their re spective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2014 C 2015 analog devices, inc. all rights reserved. features jesd204b (subclass 1) coded serial digital outputs 1.65 w total power per channel at 1 gsps (default settings) sfdr at 1 gsps = 85 dbfs at 340 mhz, 80 dbfs at 1 ghz snr at 1 gsps = 65.3 dbfs at 340 mhz (a in = ?1.0 dbfs), 60.5 dbfs at 1 ghz (a in = ?1.0 dbfs) enob = 10.8 bits at 10 mhz dnl = 0.5 lsb inl = 2.5 lsb noise density = ?154 dbfs/hz at 1 gsps 1.25 v, 2.5 v, and 3.3 v dc supply operation no missing codes internal adc voltage reference flexible input range: 1.46 v p - p to 1.94 v p - p ad9680 - 1250 : 1.58 v p - p nominal ad9680 - 1000 and ad9680 - 820 : 1.70 v p - p nominal ad9680 - 500 : 1.46 v p - p to 2.06 v p - p (2.06 v p - p nominal) programmable termination impedance 400 , 200 , 100 , and 50 diffe rential 2 ghz usable analog input full power bandwidth 95 db channel isolation/crosstalk amplitude detect bits for efficient agc implementation 2 integrated wideband digital processors per channel 12- bit nco, up to 4 half - band filters differential clock input integer clock divide by 1, 2, 4, or 8 flexible jesd204b lane configurations small signal dither applications communications diversity multiband, multimode digital receivers 3g/4g, td - scdma, w - cdma, gsm, lte general - purpose software radios ultrawideba nd satellite receivers instrumentation radars signals intelligence (sigint) docsis 3.0 cmts upstream receive paths hfc digital reverse path receivers functional block dia gram vin+a vin?a vin+b vin?b clk+ clk? ad9680 serdout0 serdout1 serdout2 serdout3 2 4 sysref clock generation 14 14 pdwn/ stby syncinb fd_a fd_b buffer buffer jesd204b high speed serializer tx outputs jesd204b subclass 1 control v_1p0 8 agnd drgnd dgnd sdio sclk csb avdd1 (1.25v) avdd2 (2.5v) avdd3 (3.3v) avdd1_sr (1.25v) dvdd (1.25v) drvdd (1.25v) spivdd (1.8v to 3.3v) 4 fast detect fast detect signal monitor signal monitor adc core adc core spi control ddc ddc 11752-001 control registers figure 1. product highlights 1. wide full power bandwidth supports if sampling of signals up to 2 ghz. 2. buffered inputs with programmable input termination eases filter design and implementation. 3. four integrated wideband decimation filters and numerically controlled oscillator (nco) blocks supporting mul tiband receivers. 4. flexible serial port interface (spi) controls various product features and functions to meet specific system requirements. 5. programmable fast overrange detection. 6. 9 mm 9 mm, 64 - lead lfcsp.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 2 of 97 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 3 general description ......................................................................... 4 specifications ..................................................................................... 5 dc specifications ......................................................................... 5 ac specifications .......................................................................... 6 digital specifications ................................................................... 8 switching specifications .............................................................. 9 timing specifications ................................................................ 10 absolute maximum ratings .......................................................... 12 thermal characteristics ............................................................ 12 esd caution ................................................................................ 12 pin configuration and function descriptions ........................... 13 typical performance characteristics ........................................... 15 ad9680 - 1250 .............................................................................. 15 ad9680 - 1000 .............................................................................. 19 ad9680 - 820 ................................................................................ 24 ad9680 - 500 ................................................................................ 29 equivalent circuits ......................................................................... 33 theory of operation ...................................................................... 35 adc architecture ...................................................................... 35 analog input considerations .................................................... 35 voltage reference ....................................................................... 41 clock input considerations ...................................................... 42 adc overrange and fast detect .................................................. 44 adc overrange .......................................................................... 44 fast threshold detection (fd_a and fd_b) ........................ 44 signal monitor ................................................................................ 45 sport over jesd204b ............................................................. 46 digital downconverter (ddc) ..................................................... 48 ddc i/q input selection .......................................................... 48 ddc i/q output selection ....................................................... 48 ddc general description ........................................................ 48 frequency translation ................................................................... 54 frequency translation general description .............................. 54 ddc nco plus mixer loss and sfdr ................................... 55 numerically controlled oscillator .......................................... 55 fir filters ........................................................................................ 57 fir filters general description ............................................... 57 half - band filters ........................................................................ 58 ddc gain stage ......................................................................... 60 ddc complex to real conversion ......................................... 60 ddc example configurations ................................................. 61 digital outputs ............................................................................... 64 introducti on to the jesd204b interface ................................. 64 jesd204b overview .................................................................. 64 functional overview ................................................................. 65 jesd204b link establishment ................................................. 65 physical layer (driver) outputs .............................................. 67 jesd204b tx converter mapping ........................................... 69 configuring the jesd204b link .............................................. 71 multichip synchronization ............................................................ 74 sysref setup/hold window monitor ................................. 76 test modes ....................................................................................... 78 adc test modes ........................................................................ 78 jesd204b block test modes .................................................... 79 serial port interface ........................................................................ 81 configuration using the spi ..................................................... 81 hardware interface ..................................................................... 81 spi accessible features .............................................................. 81 memory map .................................................................................. 82 reading the memory map register table ............................... 82 memory map register table ..................................................... 83 ap plications information .............................................................. 96 power supply recommendations ............................................. 96 exposed pad thermal heat slug recommendations ............ 96 avdd1_sr (pin 57) and agnd (pin 56 and pin 60) .............. 96 outline dimensions ....................................................................... 97 ordering g uide .......................................................................... 97
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 3 of 97 revision history 1 1 /15 rev. b to rev. c added ad9680 - 1250 ......................................................... universal changes to features section ............................................................ 1 change to general description section ......................................... 4 changes to table 1 ............................................................................ 5 changes to table 2 ............................................................................ 6 changes to table 4 ............................................................................ 9 changes to table 5 .......................................................................... 10 changes to figure 4 ......................................................................... 11 changes to pin 14 description, table 8 ....................................... 14 added ad9680 - 1250 section and figure 6 to figure 29; renumbered sequentially .............................................................. 15 chan ges to figure 113 .................................................................... 34 changes to analog i nput considerations section ...................... 35 changes to table 9 .......................................................................... 36 changes to input buffer control registers (0x018, 0x019, 0x01a, 0x935, 0x934, 0x11a) section .......................................... 37 added figure 118 to figure 120 .................................................... 37 changes to table 10 ........................................................................ 40 changes to table 17 ........................................................................ 57 changes to adc test modes section ........................................... 78 changes to table 36 ........................................................................ 83 changes to ordering guide ........................................................... 97 3/15 rev. a to rev. b added ad9680 - 820 ........................................................... universal changes to features section ............................................................ 1 changes to table 1 ............................................................................ 5 changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 8 changes to table 4 ............................................................................ 9 added figure 14; renumbered sequentially ............................... 15 added a d9680 - 820 section and figure 31 through figure 36 ... 19 added figure 37 through figure 42 ............................................ 20 added figure 43 through figure 48 ............................................ 21 added figure 49 through figure 54 ............................................ 22 added figure 55 .............................................................................. 23 changes to f igure 69 and figure 70 ............................................. 26 changes to input buffer control registers (0x018, 0x019, 0x01a, 0x935, 0x934, 0x11a) section, table 9, and figure 93 .................... 31 added figure 99 through figure 100 .......................................... 33 changes to table 10 ........................................................................ 34 changes to clock jitter considerations section ......................... 37 added figure 112 ............................................................................ 37 changes to digital downconverter (ddc) section ................... 42 changes to table 17 ........................................................................ 51 changes to table 36 ........................................................................ 77 changes to ordering guide ........................................................... 91 12/14 rev. 0 to rev. a added ad9680 - 500 ........................................................... universal changes to features section and figure 1 ..................................... 1 changes to general description section ....................................... 4 changes to specifications section and table 1 ............................. 5 changes to ac specifications section and table 2 ....................... 6 changes to digital specifications section ..................................... 8 changes to switching specifications section and table 4 ........... 9 changes to table 6, therm al characteristics section, and table 7 ............................................................................................... 11 change to digital inputs description, table 8 ............................ 13 added ad9680 - 1000 section, figure 10, and figure 11; renumbered sequentially .............................................................. 14 changes to figure 6 to figure 9 .................................................... 14 added figure 12 to figure 14 ........................................................ 15 changes to figure 15 to figure 17 ................................................ 15 changes to figure 18 to figure 21 ................................................ 16 changes to figure 25 and figure 29 ............................................. 17 changes to figure 30 ...................................................................... 18 deleted figure 35, figure 36, and figure 38 ................................ 19 added ad9680 - 500 section and figure 31 to figure 54 ............. 19 changes to analog input considerati ons section and differential input configurations section ................................... 25 added input buffer control registers (0x018, 0x019, 0x01a, 0x935, 0x934, 0x11a) section, figure 66, figure 68, and table 9; renumbered sequentially .............................................................. 26 changes to analog input buffer controls and sfdr optimization section and figure 67 ............................................ 26 added figure 69 to figure 72 ........................................................ 27 added figure 73 to figure 75 ........................................................ 28 changes to table 10 ........................................................................ 28 added input clock divider ? period delay adjust section and clock fine delay adjust section ................................................... 30 changes to figure 83 and temperature diode section ............. 31 added signal monitor section and figure 86 to figure 89 ....... 33 changes to table 11 ........................................................................ 39 changes to table 12 to table 14 .................................................... 40 changes to table 16 ........................................................................ 41 deleted figure 65 and figure 66 ................................................... 45 changes to table 17 ........................................................................ 45 changes to table 19 to table 20 .................................................... 46 changes to table 22 ........................................................................ 47 changes to table 23 ........................................................................ 49 changes to jesd204b link establishment section ................... 53 added figure 105 to figure 110 .................................................... 56 changes to example 1: full bandwidth mode section .............. 60 added multichip synchronization section, figure 115 to figure 117, and table 28 ................................................................. 62 added test modes section and table 29 to table 33 ................. 66 changes to reading the memory map register table section ....... 70 changes to table 36 ........................................................................ 71 changes to power supply recommendations section, figure 118, and exposed pad thermal heat slug recommend ations section ............................................................ 83 changes to ordering guide ........................................................... 84 5/14 revision 0: initial version
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 4 of 97 general description the ad9680 is a dual, 14 - bit, 1.25 gsps/1 gsps/820 msps/ 500 msps analog - to - digital converter (adc). the device has an on - chip buffer and sample - and - hold circuit designed for low power, small size , and ease of use. this device is designed for sampling wide bandwidth analog signals of up to 2 ghz. the ad9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. the dual adc cores feature a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth inputs supporting a variety of user - selectable input ranges. an inte grated voltage reference eases design considerations. the analog input and clock signals are differential inputs. each adc data output is internally connected to two digital down - converters (ddcs). each ddc consists of up to five cascaded signal processing stages: a 12 - bit frequency translator (nco), and four half - band decimation filters. the ddcs are bypassed by default. in addition to the ddc blocks, the ad9680 has several functions that simplif y the automatic gain control (agc) function in the communications receiver. the programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the adc. if the input signal level exceeds the programmable threshold, the fast detect indicator goes high. because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the adc input. users can configure the subclass 1 jesd204b - based high speed serialized output in a variety of one - , two - , or four - lane configurations, depending on the ddc configuration and the acceptable lane rate of the receiving logic device. multiple device synchronization is supported through the sysref and syncinb input pi ns. the ad9680 has flexible power - down options that allow significant power savings when desired. all of these features can be programmed using a 1.8 v to 3.3 v capable , 3 - wire spi. the ad9680 is available in a pb - free, 64 - lead lfcsp and is specified over the ?40c to +85c industrial temperature range. this product is protected by a u.s. patent.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 5 of 97 specifica tions dc specifications avdd1 = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, specified maximum sampling rate for each speed grade, a in = ?1.0 dbfs, clock divider = 2, default spi settings, t a = 25c, unless otherwise noted. table 1 . ad9680 - 500 ad9680 - 820 ad9680 - 1000 ad9680 - 1250 parameter temp min typ max min typ max min typ max min typ max unit resolution full 14 14 14 14 bits accuracy no missing codes full guaranteed guaranteed guaranteed guaranteed offset error full ?0.3 0 +0.3 ?0.3 0 +0.3 ?0.31 0 +0.31 ?0.31 0 +0.31 % fsr offset matching full 0 0.3 0 0.23 0 0.23 0 0.3 % fsr gain error full ?6 0 +6 ?6 0 +6 ?6 0 +6 ?6 0 +6 % fsr gain matching full 1 5.1 1 5.5 1 4.5 1 4.5 % fsr differential nonlinearity (dnl) full ?0.6 0.5 +0.7 ?0.7 0.5 +0.8 ?0.7 0.5 +0.8 ?0.8 0.5 +0.8 lsb integral nonlinearity (inl) full ?4.5 2.5 +5.0 ?3.3 2.5 +4.3 ?5.7 2.5 +6.9 ?6 3 +6 lsb temperature drift offset error full ?3 ? 10 ?12 ?1 5 ppm/c gain error full 25 54 13.8 92 ppm/c internal voltage reference vol tage full 1.0 1.0 1.0 1.0 v input - referred noise v ref = 1.0 v 25c 2.06 2.46 2.63 3.45 lsb rms analog inputs differential input voltage range (programmable) full 1.46 2.06 2.06 1.46 1.70 1.94 1.46 1.70 1.94 1.46 1.58 1.94 v p - p common - mode voltage (v cm ) 25c 2.05 2.05 2.05 2.05 v differential input capacitance 1 25c 1.5 1.5 1.5 1.5 pf analog input full power bandwidth 25c 2 2 2 2 ghz power supply avd d1 full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 v avdd2 full 2.44 2.50 2.56 2.44 2.50 2.56 2.44 2.50 2.56 2.44 2.50 2.56 v avdd3 full 3.2 3.3 3.4 3.2 3.3 3.4 3.2 3.3 3.4 3.2 3.3 3.4 v avdd1_sr full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 v dvdd full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 v drvdd full 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 1.22 1.25 1.28 v spivdd full 1.7 1.8 3.4 1.7 1.8 3.4 1.7 1.8 3.4 1.7 1.8 3.4 v i avdd1 full 435 467 605 660 685 720 785 880 ma i avdd2 full 395 463 490 545 595 680 675 780 ma i avdd3 full 87 101 125 140 125 142 125 142 ma i avdd1_sr full 15 22 15 18 16 18 17 20 ma i dvdd 2 full 145 152 205 246 208 269 250 325 ma i drvdd 1 full 190 237 200 240 200 225 220 300 ma i drvdd (l = 2 mode) 25c 140 n/a 3 n/a 3 n/a 3 ma i s pivdd full 5 6 5 6 5 6 5 6 ma
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 6 of 97 ad9680 - 500 ad9680 - 820 ad9680 - 1000 ad9680 - 1250 parameter temp min typ max min typ max min typ max min typ max unit power consumption total power dissipation (including output drivers) 2 full 2.2 2.9 3.3 3.7 w total pow er dissipation ( l = 2 mode ) 25c 2.1 n/a 3 n/a 3 n/a 3 w power - down dissipation full 700 820 835 1030 mw standby 4 full 1.2 1.3 1.4 1.66 w 1 all lanes running. power dissipation on drvdd changes with lane rate and number of lanes used. 2 default mode. no ddcs used. l = 4, m = 2, f = 1. 3 n/a means not applicable. at the maximum sample rate, it is not applicable to use l = 2 mode on the jesd204b output interface because this exceeds the maximum lane rate of 12.5 gbps. l = 2 mode is support ed when the equation ((m n? (10/8) f out )/l) results in a line rate that is 12.5 gbps. f out is the output sample rate and is denoted by f s /dcm, where dcm is the decimation ratio. 4 can be controlled by the spi. ac specifications avdd1 = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, specified maximum sampling rate for each speed grade, a in = ?1.0 dbfs, clock divider = 2, default spi settings, t a = 25c, unless otherwise noted. table 2 . ad9680 - 500 ad9680 - 820 ad9680 - 1000 ad9680 - 1250 parameter 1 temp min typ max min typ max min typ max min typ max unit analog input full scale full 2.06 1.7 1.7 1.58 v p -p noise density 2 full ?153 ?153 ?154 ?151.5 dbfs/hz signal - to - noise ratio (snr) 3 f in = 10 mhz 25c 69.2 67.2 67.2 63.6 dbfs f in = 170 mhz full 67.8 69.0 65.6 67.0 65.1 66.6 61.5 63.2 dbfs f in = 340 mhz 25c 68.6 66.5 65.3 62.8 dbfs f in = 450 mhz 25c 68.0 65.1 64.0 62.2 dbfs f in = 765 mhz 25c 64.4 64.0 61.5 61.1 dbfs f in = 985 mhz 25c 63.8 63.4 60.5 59.2 dbfs f in = 1950 mhz 25c 60.5 59.7 57.0 55.5 dbfs snr and distortion ratio (sinad) 3 f in = 10 mhz 25c 69.0 67.1 67.1 63.5 dbfs f in = 170 mhz full 67.6 68.8 65.2 66.8 65.0 66.4 61.4 62.8 dbfs f in = 340 mhz 25c 68.4 66.3 65.2 62.6 dbfs f in = 450 mhz 25c 67.9 64.7 63.8 61.8 dbfs f in = 765 mhz 25c 64.2 63.5 62.1 60.8 dbfs f in = 985 mhz 25c 63.6 62.7 61.1 58.2 dbfs f in = 1950 mhz 25c 60.3 58.7 56.0 51.5 dbfs effective number of bits (enob) f in = 10 mhz 25c 11.2 10.9 10.8 10.3 bits f in = 170 mhz full 10.9 11.1 10.5 10.8 10.5 10.7 9.9 10.1 bits f in = 340 mhz 25c 11.1 10.7 10.5 10.1 bits f in = 450 mhz 25c 11.0 10.5 10.3 10.0 bits f in = 765 mhz 25c 10.4 10.3 10.0 9.8 bits f in = 985 mhz 25c 10.3 10.1 9.8 9.4 bits f in = 1950 mhz 25c 9.7 9.5 9.0 8.3 bits
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 7 of 97 ad9680 - 500 ad9680 - 820 ad9680 - 1000 ad9680 - 1250 parameter 1 temp min typ max min typ max min typ max min typ max unit spurious - free dynamic range (sfdr) 3 f in = 10 m hz 25c 83 91 88 84 dbfs f in = 170 mhz full 80 88 75 83 75 85 74 77 dbfs f in = 340 mhz 25c 83 81 85 78 dbfs f in = 450 mhz 25c 81 78 82 76 dbfs f in = 765 mhz 25c 80 78 82 77 dbfs f in = 985 mhz 25c 75 74 80 71 dbfs f in = 1950 mhz 25c 70 70 68 61 dbfs worst harmonic, second or third 3 f in = 10 mhz 25c ?83 ?91 ?88 ?84 dbfs f in = 170 mhz full ?88 ?80 ?83 ?75 ?85 ?75 ?77 ? 74 dbfs f in = 340 mhz 25c ?83 ?81 ?85 ?78 dbfs f in = 450 mhz 25c ?81 ?78 ?82 ?76 dbfs f in = 765 mhz 25c ?80 ?78 ?82 ?77 dbfs f in = 985 mhz 25c ?75 ?74 ?80 ?71 dbfs f in = 1950 mhz 25c ?70 ?70 ?68 ?61 dbfs worst other, excluding second or third harmonic 3 f in = 10 mhz 25c ? 95 ?97 ?95 ?87 dbfs f in = 170 mhz full ? 95 ? 82 ?93 ?80 ?94 ?81 ?79 ? 74 dbfs f in = 340 mhz 25c ? 93 ?91 ?88 ?81 dbfs f in = 450 mhz 25c ? 93 ?90 ?86 ?79 dbfs f in = 765 mhz 25c ? 88 ?83 ?81 ?79 dbfs f in = 985 mhz 25c ? 89 ?84 ?82 ?77 dbfs f in = 1950 mhz 25c ? 84 ?74 ?75 ?69 dbfs two - tone intermodulation distortion (imd), a in1 and a in2 = ?7 dbfs f in1 = 185 mhz, f in2 = 188 mhz 25c ?88 ?90 ?87 ?82 dbfs f in1 = 338 mhz, f in2 = 341 mhz 25c ?88 ?87 ?88 ?78 4 dbfs crosstalk 5 25c 95 95 95 95 db full power bandwidth 6 25c 2 2 2 2 ghz 1 see the an - 835 application note, understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 noise density is measured at a low analog input frequency (30 mhz). 3 see table 10 for the recommended settings for full - scale voltage and buffer current setting s. 4 measurement taken with 449 mhz and 452 mhz inputs for two - tone. 5 crosstalk is measured at 170 mhz with a ?1.0 dbfs analog input on one channel and no input on the adjacent channel. 6 measured with the circuit shown in figure 115.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 8 of 97 digital specificatio ns avdd1 = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvd d = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, specified maximum sampling rate for each speed grade, a in = ?1.0 dbfs, clock divider = 2, default spi settings, t a = 25c, unless otherwise noted. table 3 . parameter temperature min typ max unit clock inputs (clk+, clk?) logic compliance full lvds/lvpecl differential input voltage full 600 1200 1800 mv p -p input common - mode voltage full 0.85 v input resistance (differential) full 35 k? input capacitance full 2.5 pf sysref inputs (sysref+, sysref?) logic compliance full lvds/lvpecl differential input voltage full 400 1200 1800 mv p -p input common - mode voltage full 0.6 0.85 2.0 v input resistance (differential) full 35 k? input capacitance (differential) full 2.5 pf logic inputs (sdi, sclk, csb, pdwn/stby) logic compliance full cmos logic 1 voltage full 0.8 spivdd v logic 0 voltage full 0 0.5 v input resistance full 30 k? logic output (sdio) logic compliance full cmos logic 1 voltage (i oh = 800 a) full 0.8 spivdd v logic 0 voltage (i ol = 50 a) full 0 0.5 v syncin input (syncinb+/syncinb?) logic compliance full lvds/lvpecl/cmos differential input voltage full 400 1200 1800 mv p -p input common - mode voltage full 0.6 0.85 2.0 v input resistance (differential) full 35 k? input capacitance full 2.5 pf logic outputs (fd_a, fd_b) logic compliance full cmos logic 1 voltage full 0.8 spivdd v logic 0 voltage full 0 0.5 v input resistance full 30 k? digital outputs (serdoutx, x = 0 to 3) logic compliance full cml differential output voltage full 360 770 mv p -p output common - mode voltage (v cm ) ac - coupled 25c 0 1.8 v short - circuit current (i dshort ) 25c ?100 +100 ma differential return loss (rl diff ) 1 25c 8 db common - mode return loss (rl cm ) 1 25c 6 db differential termination impedance full 80 100 120 ? 1 differential and common - mode return loss are measured from 100 mhz to 0.75 baud rate.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 9 of 97 switching specificat ions avdd1 = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, specified maximum sampling rate for each speed grade, a in = ?1.0 dbfs, default spi settings, t a = 25c, unless otherwise noted. table 4 . ad9680 - 500 ad9680 - 820 ad9680 - 1000 ad9680 - 1250 parameter temp min typ max min typ max min typ max min typ max unit clock clock rate (at clk+/clk? pins) full 0.3 4 0.3 4 0.3 4 0.3 4 ghz maximum sample rate 1 full 500 820 1000 1250 msps minimum sample rate 2 full 300 300 300 300 msps clock pulse width high full 1000 609.7 500 400 ps clock pulse width low full 1000 609.7 500 400 ps output parameters unit interval (ui) 3 full 80 200 80 121.95 80 100 80 80 ps rise time (t r ) (20% to 80% into 100 ? load) 25c 24 32 24 32 24 32 24 32 ps fall time (t f ) (20% to 80% into 100 ? load) 25c 24 32 24 32 24 32 24 32 ps pll lock time 25c 2 2 2 2 ms data rate per channel (nrz) 4 25c 3.125 5 12.5 3.125 8.2 12.5 3.125 10 12.5 3.1215 12.5 12.5 gbps latency 5 pipeline latency full 55 55 55 55 clock cycles fast detect latency full 28 28 28 28 clock cycles wake - up time 6 standby 25c 1 1 1 1 ms power - down 25c 4 4 4 4 ms aperture aperture delay (t a ) full 530 530 530 530 ps aperture uncertainty (jitter, t j ) full 55 55 55 55 f s rms out - of - range recovery time full 1 1 1 1 clock c ycles 1 the maximum sample rate is the clock rate after the divider. 2 the minimum sample rate operates at 300 msps with l = 2 or l = 1. 3 baud rate = 1/ui. a subset of this range can be supported . 4 default l = 4. this number can be changed based on the sample rate and decimation ratio. 5 no ddcs used. l = 4, m = 2, f = 1. 6 wake - up time is defined as the time required to return to normal operation from power - down mode.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 10 of 97 timing specification s table 5 . parameter test conditions/comments min typ max unit clk+ to sysref+ timing requirements see figure 3 t su_sr device clock to sysref+ setup time 117 ps t h_sr device clock to sysref+ hold time ?96 ps spi timing requirements see figure 4 t ds setup time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk must be in a logic high state 10 ns t low minimum period that sclk must be in a logic low state 10 ns t access maximum time delay between falling edge of sclk and output data valid for a read operation 6 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 4 ) 10 ns timing diagrams serdout0? n ? 54 n ? 53 n ? 52 n ? 51 n ? 1 sample n n + 1 aperture delay n ? 55 clk+ clk? clk+ clk? serdout0+ serdout1? serdout1+ serdout2? serdout2+ serdout3? serdout3+ a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j converter0 msb converter0 lsb converter1 msb converter1 lsb analog input signal 11752-002 sample n ? 55 encoded into 1 8-bit/10-bit symbol sample n ? 54 encoded into 1 8-bit/10-bit symbol sample n ? 53 encoded into 1 8-bit/10-bit symbol figure 2 . data output timing (full bandwidth mode; l = 4; m = 2; f = 1)
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 11 of 97 clk+ clk? sysref+ sysref? t su_sr t h_sr 1 1752-003 figure 3 . sysref setup and hold timing don?t care don?t care don?t care don?t care sdio sclk t s t dh t clk t ds t access t h r/w a14 a13 a12 a11 a10 a9 a8 a7 d7 d6 d3 d2 d1 d0 t low t high csb 1 1752-004 figure 4 . serial port interface timing diagram
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 12 of 97 absolute maximum rat ings table 6 . parameter rating electrical avdd1 to agnd 1.32 v avdd1_sr to agnd 1.32 v avdd2 to agnd 2.75 v avdd3 to agnd 3.63 v dvdd to dgnd 1.32 v drvdd to drgnd 1.32 v spivdd to agnd 3.63 v agnd to drgnd ?0.3 v to +0.3 v vin x to agnd 3.2 v sclk, sdio, csb to agnd ?0.3 v to spivdd + 0.3 v pdwn/stby to agnd ?0.3 v to spivdd + 0.3 v operating temperature range ?40c to +85c junction temperature range ?40c to +115c storage temperature range (ambient) ?65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal characterist ics typical ja , jb , and jc are specified vs. the number of printed circuit board (pcb) layers in different airflow velocities (in m/sec). airflow increases heat dissipation effectively reducing ja and jb . in addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes, reduces ja . thermal performance for actual applications requires careful inspection of the conditions in an applica tion. the use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in table 6 . table 7 . thermal resistance values pcb type airflow velocity (m/sec) ja jb jc_top jc_bot unit jedec 2s2p board 0.0 17.8 1, 2 6.3 1, 3 4.7 1, 4 1.2 1, 4 c/w 1.0 15.6 1, 2 5.9 1, 3 n/a 5 c/w 2.5 15.0 1, 2 5.7 1, 3 n/a 5 c/w 1 per jedec 51 - 7, plus jedec 51 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per jedec jesd51 - 8 (still air). 4 per mil - std 883, method 1012.1. 5 n/a means not applicable. esd caution
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 13 of 97 pin configuration an d function descripti ons ad9680 top view (not to scale) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 fd_a drgnd drvdd syncinb? syncinb+ serdout0? serdout0+ serdout1? serdout1+ serdout2? serdout2+ serdout3? serdout3+ drvdd drgnd fd_b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 avdd1 avdd2 avdd2 avdd1 agnd sysref? sysref+ avdd1_sr agnd avdd1 clk? clk+ avdd1 avdd2 avdd2 avdd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd1 avdd1 avdd2 avdd3 vin?a vin+a avdd3 avdd2 avdd2 avdd2 avdd2 v_1p0 spivdd pdwn/stby dvdd dgnd avdd1 avdd1 avdd2 avdd3 vin?b vin+b avdd3 avdd2 avdd2 avdd2 spivdd csb sclk sdio dvdd dgnd 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 notes 1. exposed pad. the exposed thermal pad on the bottom of the package provides the ground refence for avddx. this exposed pad must be connected to ground for proper operation. 11752-005 figure 5 . pin configuration (top view) table 8 . pin function descriptions pin no. mnemonic type description power supplies 0 epad ground exposed pad. the exposed thermal pad on the bottom of the package provides the ground reference for avddx. this exposed pad must be connected to ground for proper operation. 1, 2, 47, 48, 49, 52, 55, 61, 64 avdd1 supply analog power supply (1.25 v nominal). 3, 8, 9, 10, 11, 39, 40, 41, 46, 50, 51, 62, 63 avdd2 supply analog power supply (2.5 v nominal). 4, 7, 42, 45 avdd3 supply analog power supply (3.3 v nominal). 13, 38 spivdd supply digital power supply for spi (1.8 v to 3.3 v). 15, 34 dvdd supply digital power supply (1.25 v nominal). 16, 33 dgnd ground ground reference for dvdd. 18, 31 drgnd ground ground reference for drvdd. 19, 30 drvdd supply digital driver power supply (1.25 v nominal). 56, 60 agnd 1 ground ground reference for sysref. 57 avdd1_sr 1 supply analog power supply for sysref (1.25 v nominal). analog 5, 6 vin?a, vin+a input adc a analog input complement/true. 12 v_1p0 input/dnc 1.0 v reference voltage input/do not connect. this pin is configurable through the spi as a no connect or an input. do not connect this pin if using the internal reference. requires a 1.0 v reference voltage input if using an external voltage reference sou rce. 44, 43 vin?b, vin+b input adc b analog input complement/true. 53, 54 clk+, clk? input clock input true/complement.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 14 of 97 pin no. mnemonic type description cmos outputs 17, 32 fd_a, fd_b output fast detect outputs for channel a and channel b. digital inputs 20, 21 syncinb?, syncinb+ input active low jesd204b lvds sync input true/complement. 58, 59 sysref+, sysref? input active high jesd204b lvds system reference input true/complement. data outputs 22, 23 serdout0?, serdout0+ output lane 0 output data complement/true. 24, 25 serdout1?, serdout1+ output lane 1 output data complement/true. 26, 27 serdout2?, serdout2+ output lane 2 output data complement/true. 28, 29 serdout3?, serdout3+ output lane 3 output data complement/true. device under test (dut) controls 14 pdwn/stby input power - down input (active high). the operation of this pin depends on the spi mode and can be configured as power - down or standby. requires an external 10 k ? pull - down resistor . 35 sdio input/output spi serial data input/output. 36 sclk input spi serial clock. 37 csb input spi chip select (active low). 1 to ensure proper a dc operation, connect avdd1_sr and agnd separate ly from the avdd1 and epad connection. for more information , see the applications information section .
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 15 of 97 typical performance characteristics ad9680 - 1250 avdd1 = 1.25 v, avdd1_sr = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, 1.58 v p - p full - scale differential input, a in = ?1.0 dbfs, default spi settings, clock divider = 2, t a = 25c, 128k fft sample, unless otherwise noted. see table 10 for recommended settings. ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 64dbfs enob = 10.3 bits sfdr = 82dbfs buffer current = 3.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-606 figure 6 . single- tone fft with f in = 10.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 63.4dbfs enob = 10.2 bits sfdr = 79dbfs buffer current = 3.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-607 figure 7 . single- tone fft with f in = 170.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 62.8dbfs enob = 10.1 bits sfdr = 76dbfs buffer current = 3.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-608 figure 8 . single- tone fft with f in = 340.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 62.5dbfs enob = 9.9 bits sfdr = 70dbfs buffer current = 3.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-609 figure 9 . single- tone fft with f in = 450.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 60.9dbfs enob = 9.8 bits sfdr = 74dbfs buffer current = 5.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-610 figure 10 . single - tone fft with f in = 765.3 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 59.7dbfs enob = 9.6 bits sfdr = 74dbfs buffer current = 5.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-6 1 1 figure 11 . single - tone fft with f in = 985.3 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 16 of 97 ?120 ?100 ?80 ?60 ?40 ?20 0 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 58.5dbfs enob = 9.3 bits sfdr = 68dbfs buffer current = 5.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-612 figure 12 . single - tone fft with f in = 1205.3 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 56.6dbfs enob = 9.0 bits sfdr = 67dbfs buffer current = 7.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-613 figure 13 . single - tone fft wit h f in = 1602.3 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 625.000 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 55.4dbfs enob = 8.8 bits sfdr = 63dbfs buffer current = 8.5 78.125 156.250 234.375 312.500 390.625 468.750 546.875 1 1752-614 figure 14 . single - tone fft with f in = 1954.3 mhz 60 85 80 75 70 65 snr/sfdr (dbfs) sample rate (mhz) snr sfdr 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 1 1752-615 figure 15 . snr/sfdr vs. f s , f in = 170.3 mhz; buffer control 1 (0x018) = 3.5 667.3 589.3 511.3 433.3 355.3 290.3 212.3 147.3 10.3 snr/sfdr (dbfs) input frequency (mhz) 60 65 70 75 80 85 3.5 snr (dbfs) 3.5 sfdr (dbfs) 4.5 snr (dbfs) 4.5 sfdr (dbfs) 1 1752-616 figure 16 . snr/sfdr vs. f in ; f in < 700 mhz; buffer control 1 (0x018) = 3.5 and 4.5 snr/sfdr (dbfs) input frequency (mhz) 55 60 65 70 75 80 snr 6.5 sfdr 6.5 628.3 706.6 784.3 862.3 940.3 1018.3 1096.3 1174.3 1252.3 1 1752-617 figure 17 . snr/sfdr vs. f in ; 65 0 mhz < f in < 1.3 ghz; buffer control 1 (0x018) = 6 . 5
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 17 of 97 snr/sfdr (dbfs) input frequency (mhz) 50 55 60 65 70 75 80 snr 8.5 sfdr 8.5 1252.3 1356.3 1460.3 1564.3 1668.3 177.23 1876.3 1980.3 1 1752-618 figure 18 . snr/sfdr vs. f in ; 1.3 ghz < f in < 2ghz; buffer control 1 (0x018) = 8.5 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) frequency (mhz) a in1 and a in2 = ?7dbfs sfdr = 82dbfs imd2 = 84dbfs imd3 = 82dbfs buffer current = 3.5 1 1752-095 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 figure 19 . two - tone fft; f in1 = 184 mhz, f in2 = 187 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) frequency (mhz) a in1 and a in2 = ?7dbfs sfdr = 78dbfs imd2 = 78dbfs imd3 = 78dbfs buffer current = 5.5 1 1752-096 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 figure 20 . two - tone fft; f in1 = 449 mhz, f in2 = 452 mhz ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?120 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 1 1752-622 figure 21 . two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184 mhz and f in2 = 187 mhz ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?140 ?120 0 ?20 ?40 ?60 ?80 ?100 imd3 (dbc) imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 1 1752-623 figure 22 . two - tone imd3/sfdr vs. input amplitude (a in ) with f in1 = 449 mhz and f in2 = 452 mhz ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 snr/sfdr (db) input amplitude (dbfs) ?40 ?20 0 20 40 60 80 100 120 snr (dbfs) snr (dbc) sfdr (dbc) sfdr (dbfs) 1 1752-624 figure 23 . snr/sf dr vs. analog input level, f in = 170.3 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 18 of 97 55 85 80 75 70 65 60 snr/sfdr (dbfs) temperature (c) ?48 ?38 ?28 ?18 ?8 2 12 22 32 42 52 62 72 82 92 102 112 snr sfdr 1 1752-625 figure 24 . snr/sfdr vs. temperature, f in = 170.3 mhz ?4 ?3 ?2 ?1 0 1 2 3 4 0 16000 inl (lsb) output code 2000 4000 6000 8000 10000 12000 14000 1 1752-626 figure 25 . inl, f in = 10.3 mhz ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 16000 dnl (lsb) output code 2000 4000 6000 8000 10000 12000 14000 1 1752-627 figure 26 . dnl, f in = 15 mhz number of hits code 0 200000 400000 600000 800000 1000000 1200000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 3.45 lsb rms 1 1752-628 figure 27 . input - referred noise histogram power (w) temperature (c) ?48 ?38 ?28 ?18 ?8 2 12 22 32 42 52 62 72 82 3.55 3.60 3.65 3.70 3.75 3.80 3.85 3.90 3.95 4.00 1 1752-629 figure 28 . power dissipation vs. temperature 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 power dissipation (w) sample rate (mhz) 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 1 1752-630 figure 29 . power dissipation vs. f s
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 19 of 97 ad9680 - 1000 avdd1 = 1.25 v, avdd1_sr = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, 1.7 v p - p full - scale differential input, a in = ?1.0 dbfs, default spi sett ings, clock divider = 2, t a = 25c, 128k fft sample, unless otherwise noted. see table 10 for recommended settings. ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 67.2dbfs enob = 10.8 bits sfdr = 88dbfs buffer control 1 = 1.5 1 1752-100 figure 30 . single - tone fft with f in = 10.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 66.6dbfs enob = 10.7 bits sfdr = 85dbfs buffer control 1 = 3.0 1 1752-101 figure 31 . single - tone fft with f in = 170.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 65.3dbfs enob = 10.5 bits sfdr = 85dbfs buffer control 1 = 3.0 1 1752-102 figure 32 . single - tone fft with f in = 340.3 mhz ?130 ?110 ?90 ?70 ?50 ?30 ?10 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 64.0dbfs enob = 10.3 bits sfdr = 82dbfs buffer control 1 = 3.0 1 1752-103 figure 33 . single - tone fft with f in = 450.3 mhz 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 61.5dbfs enob = 10.1 bits sfdr = 82dbfs buffer control 1 = 6.0 ?120 ?100 ?80 ?60 ?40 ?20 0 1 1752-104 figure 34 . single - tone fft with f in = 765.3 mhz 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 60.5dbfs enob = 9.9 bits sfdr = 80dbfs buffer control 1 = 6.0 1 1752-105 ?120 ?100 ?80 ?60 ?40 ?20 0 figure 35 . single - tone fft with f in = 985.3 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 20 of 97 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 59.8bfs enob = 9.6 bits sfdr = 79dbfs buffer control 1 = 8.0 ?120 ?100 ?80 ?60 ?40 ?20 0 1 1752-107 figure 36 . single - tone fft with f in = 1293.3 mhz 0 500 400 300 200 100 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 57.7dbfs enob = 9.2 bits sfdr = 70dbfs buffer control 1 = 8.0 1 1752-108 ?120 ?100 ?80 ?60 ?40 ?20 0 figure 37 . single - tone fft with f in = 1725.3 mhz 1 1752-506 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 100 200 300 400 500 a in = ?1dbfs snr = 57.0dbfs enob = 9.1 bits sfdr = 69dbfs buffer current = 6.0 figure 38 . single - tone fft with f in = 1950.3 mhz snr/sfdr (dbfs) sample rate (mhz) 60 65 70 75 80 85 90 1 1752-201 700 750 800 850 900 950 1000 1050 1100 snr (dbfs) sfdr (dbfs) figure 39 . snr/sfdr vs. f s , f in = 170.3 mhz; buffer control 1 (0x018) = 3.0 snr/sfdr (dbfs) 90 85 80 75 70 65 60 55 50 10.3 63.3 100.3 170.3 225.3 analog input frequenc y (mhz) 302.3 341.3 403.3 453.3 502.3 1.5 sfdr (dbfs) 1.5 snr (dbfs) 3.0 sfdr (dbfs) 3.0 snr (dbfs) 1 1752-216 figure 40 . snr/sfdr vs. f in ; f in < 500 mhz; buffer control 1 (0x018) = 1.5 and 3.0 50 100 60 70 80 90 476.8 554.4 593.2 670.8 748.4 826.0 903.6 981.2 analog input frequenc y (mhz) snr/sfdr (dbfs) 4.0 sfdr 4.0 snrfs 6.0 sfdr 6.0 snrfs 1 1752-218 figure 41 . snr/sfdr vs. f in ; 500 mhz < f in < 1 ghz; buffer control 1 (0x018) = 4.0 and 6.0
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 21 of 97 50 60 70 80 100 90 analog input frequenc y (mhz) 978.5 1065.0 1 142.4 1220.0 1297.3 1374.8 1452.2 sfdr snr snr/sfdr (dbfs) 1 1752-219 figure 42 . snr/sfdr vs. f in ; 1 ghz < f in < 1.5 ghz; buffer control 1 (0x018) = 6.0 50 60 70 100 90 80 analog input frequenc y (mhz) 1513.3 1607.4 1701.6 1795.6 1889.7 snr/sfdr (dbfs) 1 1752-220 sfdr snr figure 43 . snr/sfdr vs. f in ; 1.5 ghz < f in < 2 ghz; buffer control 1 (0x018) = 7.5 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 400 300 200 100 11752-205 a in1 and a in2 = ?7dbfs sfdr = 87dbfs imd2 = 93dbfs imd3 = 87dbfs buffer control 1 = 3.0 figure 44 . two - tone fft; f in1 = 184 mhz, f in2 = 187 mhz amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 500 400 300 200 100 11752-206 a in1 and a in2 = ?7dbfs sfdr = 88dbfs imd2 = 93dbfs imd3 = 88dbfs buffer control 1 = 4.5 figure 45 . two - tone fft; f in1 = 338 mhz, f in2 = 341 mhz ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?140 ?120 ?100 ?80 ?60 ?40 ?20 20 0 11752-207 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 46 . two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184 mhz and f in2 = 187 mhz ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 snr/sfdr (dbc and dbfs) input amplitude (dbfs) ?140 ?120 ?100 ?80 ?60 ?40 ?20 20 0 11752-208 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 47 . two - tone imd3/sfdr vs. input amplitude (a in ) with f in1 = 338 mhz and f in2 = 341 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 22 of 97 ?84 ?90 ?78 ?72 ?66 ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 snr/sfdr (db) input amplitude (dbfs) ?20 ?10 0 10 110 100 90 80 70 60 50 40 30 20 1 1752-209 sfdr (dbc) sfdr (dbfs) snr (dbfs) snr (dbc) figure 48 . snr/sfdr vs. analog input level, f in = 170.3 mhz snr/sfdr (dbfs) temperature (c) 50 100 80 90 70 60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 sfdr snr 1 1752-210 figure 49 . snr/sfdr vs. temperature, f in = 170.3 mhz inl (lsb) output code ?3 3 2 1 0 ?1 ?2 0 16000 14000 12000 10000 8000 6000 4000 2000 1 1752-2 1 1 figure 50 . inl, f in = 10.3 mhz dnl (lsb) output code ?0.6 0.6 0.4 0.2 0 ?0.2 ?0.4 0 16000 14000 12000 10000 8000 6000 4000 2000 11752-212 figure 51 . dnl, f in = 15 mhz
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 23 of 97 number of hits code 0 25000 20000 15000 10000 5000 n + 6 n + 5 n + 4 n + 3 n + 2 n + 1 n n ? 1 n ? 2 n ? 3 n ? 4 n ? 5 n ? 6 1 1752-213 2.63 lsb rms figure 52 . input - referred noise histogram power dissipation (w) temperature (c) 3.15 3.40 3.35 3.30 3.25 3.20 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 11752-214 l = 4 m = 2 f = 1 figure 53 . power dissipation vs. temperature power dissipation (w) sample rate (mhz) 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 1 1752-215 700 750 800 850 900 950 1000 1050 1100 l = 4, m = 2, f = 1 figure 54 . power dissipation vs. f s
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 24 of 97 ad9680 - 820 avdd1 = 1.25 v, avdd1_sr = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, 1.7 v p - p full - scale differential input, a in = ?1.0 dbfs, default spi settings, clock divider = 2, t a = 25c, 128k fft sample, unless otherwise noted. see table 10 for recommended settings. 1 1752-507 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 67.2dbfs enob = 10.9bits sfdr = 89dbfs buffer control 1 = 1.5 figure 55 . single - tone fft with f in = 10.3 mhz 1 1752-508 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 67.0dbfs enob = 10.8 bits sfdr = 83dbfs buffer control 1 = 2.0 figure 56 . single - tone fft with f in = 170.3 mhz 1 1752-509 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 66.5dbfs enob = 10.7 bits sfdr = 86dbfs buffer control 1 = 3.0 figure 57 . single - tone fft with f in = 340.3 mhz 1 1752-510 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 65.1dbfs enob = 10.5 bits sfdr = 79dbfs buffer control 1 = 6.5 figure 58 . single - tone fft with f in = 450.3 mhz 1 1752-5 1 1 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 64.0dbfs enob = 10.3 bits sfdr = 79dbfs buffer control 1 = 6.5 figure 59 . single - tone fft with f in = 765.3 mhz 1 1752-512 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 63.4dbfs enob = 10.1 bits sfdr = 74dbfs buffer control 1 = 8.5 figure 60 . single - tone fft with f in = 985.3 mhz
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 25 of 97 1 1752-513 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 62.0dbfs enob = 9.9 bits sfdr = 76dbfs buffer control 1 = 6.5 figure 61 . single - tone fft with f in = 1205.3 mhz 1 1752-514 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 60.5dbfs enob = 9.5 bits sfdr = 68dbfs buffer control 1 = 7.5 figure 62 . single - tone fft with f in = 1720.3 mhz 1 1752-515 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 a in = ?1dbfs snr = 59.7dbfs enob = 9.5 bits sfdr = 69dbfs buffer control 1 = 8.5 figure 63 . single - tone fft with f in = 1950.3 mhz 1 1752-516 snr/sfdr (dbfs) sample rate (mhz) 50 55 60 65 70 75 80 85 90 500 550 600 650 700 750 800 850 900 snr sfdr figure 64 . snr/sfdr vs. f s , f in = 170.3 mhz; buffer control 1 (0x018) = 3.0 1 1752-517 snr/sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 80 85 90 95 10.3 65.5 95.3 125.4 150.3 170.3 180.3 210.5 240.3 270.3 301.3 330.3 340.7 360.3 390.3 420.3 450.3 sfdr (3.0) snr (3.0) figure 65 . snr/sfdr vs. f in ; f in < 450 mhz; buffer control 1 (0x018) = 3.0 1 1752-018 snr/sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 80 85 450.3 480.3 510.3 515.3 610.3 766.3 810.3 985.3 sfdr (6.5) snr (6.5) figure 66 . snr/sfdr vs. f in ; 450 mhz < f in < 1 ghz; buffer control 1 (0x018) = 6.5
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 26 of 97 1 1752-519 snr/sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 80 985.3 1022.3 1110.3 1205.3 1315.3 1420.3 1510.3 sfdr (6.5) snr (6.5) figure 67 . snr/sfdr vs. f in ; 1 ghz < f in < 1.5 ghz; buffer control 1 (0x018) = 6.5 1 1752-520 snr/sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 1510.3 1600.3 1720.3 1810.3 1920.3 1950.3 sfdr (8.5) snr (8.5) figure 68 . snr/sfdr vs. f in ; 1.5 ghz < f in < 2 ghz; buffer control 1 (0x018) = 8.5 1 1752-529 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 ain1 and ain2 = ?7dbfs sfdr = 90dbfs imd2 = 90dbfs imd3 = 91dbfs buffer current = 3.0 figure 69 . two - tone fft; f in1 = 184 mhz, f in2 = 187 mhz 1 1752-527 amplitude (dbfs) frequency (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 0 82 164 246 328 410 ain1 and ain2 = ?7dbfs sfdr = 87dbfs imd2 = 92dbfs imd3 = 87dbfs buffer current = 3.0 figure 70 . two - tone fft; f in1 = 338 mhz, f in2 = 341 mhz 1 1752-528 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 ?87 ?81 ?75 ?69 ?63 ?57 ?51 ?45 ?39 ?33 ?27 ?21 ?15 ?9 imd3 (dbc) imd3 (dbfs) sfdr (dbc) sfdr (dbfs) figure 71 . two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184 mhz and f in2 = 187 mhz 1 1752-535 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 ?87 ?81 ?75 ?69 ?63 ?57 ?51 ?45 ?39 ?33 ?27 ?21 ?15 ?9 imd3 (dbc) imd3 (dbfs) sfdr (dbc) sfdr (dbfs) figure 72 . two - tone imd3/sfdr vs. input amplitude (a in ) with f in1 = 338 mhz and f in2 = 341 mhz
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 27 of 97 1 1752-521 snr/sfdr (dbc and dbfs) input amplitude (dbfs) ?30 ?15 0 15 30 45 60 75 90 105 120 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 snr (dbc) snr (dbfs) sfdr (dbc) sfdr (dbfs) figure 73 . snr/sfdr vs. analog input level, f in = 170.3 mhz 1 1752-533 snr/sfdr (dbfs) temperature (c) 60 65 70 75 80 85 90 ?45 ?30 ?15 ?5 5 15 25 45 65 85 snr (dbfs) sfdr (dbfs) figure 74 . snr/sfdr vs. temperature, f in = 170.3 mhz 1 1752-534 inl (lsb) output code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 2000 4000 6000 8000 10000 12000 14000 16000 figure 75 . inl, f in = 10.3 mhz 1 1752-530 dnl (lsb) output code ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0 2000 4000 6000 8000 10000 12000 14000 16000 figure 76 . dnl, f in = 15 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 28 of 97 1 1752-531 number of hits code 0 200000 400000 600000 800000 1000000 1200000 1400000 1600000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 2.46 lsb rms figure 77 . input - referred noise histogram 1 1752-532 power (w) temperature (c) 2.76 2.78 2.80 2.82 2.84 2.86 2.88 2.90 ?45 ?30 ?15 ?5 5 15 25 45 65 85 figure 78 . power dissipation vs. temperature 1 1752-522 power (w) sample rate (mhz) 2.5 2.6 2.7 2.8 2.9 3.0 3.1 500 525 550 575 600 625 650 675 700 725 750 775 800 825 850 875 900 figure 79 . power dissipation vs. f s ; l = 4, m = 2, f = 1 for f s 625 msps and l = 2, m = 2, f = 2 for f s < 625 msps (default spi)
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 29 of 97 ad9680 - 500 avdd1 = 1.25 v, avdd1_sr = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, dvdd = 1.25 v, drvdd = 1.25 v, spivdd = 1.8 v, 2.06 v p - p full - scale differential input, a in = ?1.0 dbfs, default spi settings, clock divider = 2, t a = 25c, 128k fft sample, unless otherwise noted. see table 10 for recommended settings. 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 68.9dbfs enob = 10.9 bits sfdr = 83dbfs buffer contro l 1 = 2.0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1 1752-132 figure 80 . single - tone fft with f in = 10.3 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 68.9dbfs enob = 1 1 bits sfdr = 88dbfs buffer contro l 1 = 2.0 1 1752-133 figure 81 . single - tone fft with f in = 170.3 mhz 0 25 50 75 100 125 150 175 200 225 250 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 68.5dbfs enob = 10.9 bits sfdr = 83dbfs buffer contro l 1 = 4.5 1 1752-134 figure 82 . single - tone fft with f in = 340.3 mhz 0 25 50 75 100 125 150 175 200 225 250 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 67.8dbfs enob = 10.8 bits sfdr = 83dbfs buffer contro l 1 = 4.5 1 1752-135 figure 83 . single - tone fft with f in = 450.3 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 64.7dbfs enob = 10.4 bits sfdr = 80dbfs buffer control 1 = 5.0 11752-136 figure 84 . single - tone fft with f in = 765.3 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequency (mhz) a in = ?1dbfs snr = 64.0dbfs enob = 10.3 bits sfdr = 76dbfs buffer control 1 = 5.0 11752-137 figure 85 . single - tone fft with f in = 985.3 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 30 of 97 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 63.0dbfs enob = 10.0 bits sfdr = 69dbfs buffer control 1 = 8.0 1 1752-138 figure 86 . single - tone fft with f in = 1310.3 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 61.5dbfs enob = 9.8 bits sfdr = 69dbfs buffer control 1 = 8.0 1 1752-139 figure 87 . single - tone fft with f in = 1710.3 mhz ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 25 50 75 100 125 150 175 200 225 250 amplitude (dbfs) frequenc y (mhz) a in = ?1dbfs snr = 60.8dbfs enob = 9.6 bits sfdr = 68dbfs buffer control 1 = 8.0 1 1752-140 figure 88 . single - tone fft with f in = 1950.3 mhz 60 65 70 75 80 85 90 95 300 320 340 360 380 400 sample frequenc y (mhz) snr/sfdr (dbfs) 420 440 460 480 500 530 550 sfdr snr 1 1752-141 figure 89 . snr/sfdr vs. f s , f in = 170.3 mhz; buffer control 1 = 2.0 50 60 70 80 90 100 10.3 95.3 150.3 180.3 240.3 301.3 340.7 390.3 450.3 snr/sfdr (dbfs) analog input frequenc y (mhz) 1 1752-142 2.0 snr 2.0 sfdr 4.5 snr 4.5 sfdr figure 90 . snr/sfdr vs. f in ; f in < 500 mhz; buffer control 1 (0x018) = 2.0 and 4.5 50 60 70 80 90 100 snr/sfdr (dbfs) 450.3 480.3 510.3 515.3 610.3 765.3 810.3 985.3 1010.3 analog input frequenc y (mhz) 4.0 snr 4.0 sfdr 8.0 snr 8.0 sfdr 1 1752-143 figure 91 . snr/sfdr vs. f in ; 500 mhz < f in < 1 ghz; buffer control 1 (0x018) = 4.0 and 8.0
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 31 of 97 snr/sfdr (dbfs) 50 60 65 55 70 75 80 1010.3 1205.3 1410.3 1600.3 1810.3 1950.3 analog input frequenc y (mhz) 7.0 snr 7.0 sfdr 8.0 snr 8.0 sfdr 1 1752-144 figure 92 . snr/sfdr vs. f in ; 1 ghz < f in < 2 ghz; buffer control 1 (0x018) = 7.0 and 8.0 ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 amplitude (dbfs) frequenc y (mhz) a in1 and a in2 = ?7dbfs sfdr = 88dbfs imd2 = 94dbfs imd3 = 88dbfs buffer contro l 1 = 2.0 1 1752-146 figure 93 . two - tone fft; f in1 = 184 mhz, f in2 = 187 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 50 100 150 200 250 amplitude (dbfs) frequenc y (mhz) a in1 and a in2 = ?7dbfs sfdr = 88dbfs imd2 = 88dbfs imd3 = 89dbfs buffer contro l 1 = 4.5 1 1752-147 figure 94 . two - tone fft; f in1 = 338 mhz, f in2 = 341 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 ? 90 ? 84 ? 78 ? 72 ? 66 ? 60 ? 54 ? 48 ? 42 ? 36 ? 30 ? 24 ? 18 ? 12 sfdr/imd3 (dbc and dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 1 1752-148 figure 95 . two - tone sfdr/imd3 vs. input amplitude (a in ) with f in1 = 184 mhz and f in2 = 187 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?81 ?72 ?63 ?54 ?45 ?36 ?27 ?18 ?9 sfdr/imd3 (dbc and dbfs) amplitude (dbfs) 1 1752-149 sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) figure 96 . two - tone imd3/sfdr vs. input amplitude (a in ) with f in1 = 338 mhz and f in2 = 341 mhz ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 1 10 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 snr/sfdr (dbc and dbfs) input amplitude (dbfs) 1 1752-150 sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (dbc) figure 97 . snr/sfdr vs. analog input level, f in = 170.3 mhz
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 32 of 97 1 1752-151 65 70 75 80 85 90 95 ?40 ?15 10 35 60 85 snr/sfdr (dbfs) temper a ture (c) s fd r s n r figure 98 . snr/sfdr vs. temperature, f in = 170.3 mhz ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 0 2000 4000 6000 8000 10000 12000 14000 16000 inl (lsb) output code 11752-152 figure 99 . inl, f in = 10.3 mhz ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 2000 4000 6000 8000 10000 12000 14000 16000 dn l (lsb) output code 1 1752-153 figure 100 . dnl, f in = 15 mhz 0 100000 200000 300000 400000 500000 600000 700000 800000 900000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 number of hits output code 2.06 lsb rms 1 1752-154 figure 101 . input - referred noise histogram 2.20 2.22 2.24 2.26 2.28 2.30 2.32 ?45 ?35 ?5 15 25 45 65 85 power (w) temper a ture (c) 1 1752-155 l = 4 m = 2 f = 1 figure 102 . power dissipation vs. temperature 1.87 1.92 1.97 2.02 2.07 2.12 2.17 2.22 2.27 2.32 2.37 300 320 340 360 380 400 420 440 460 480 500 520 540 power (w) sample r a te (mhz) 1 1752-156 l = 4, m = 2, f = 1 l = 2, m = 2, f = 2 figure 103 . power dissipation vs. f s
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 33 of 97 equivalent circuits a in control (spi) 10pf vin+x vin?x avdd3 avdd3 avdd3 v cm buffer 400 200 200 67 28 200 200 67 28 avdd3 avdd3 1.5pf 3pf 1.5pf 3pf 1 1752-0 1 1 figure 104 . analog inputs clk+ clk? avdd1 25? avdd1 25? 20k? 20k? v cm = 0.85v 1 1752-012 figure 105 . clock inputs sysref+ avdd1_sr 1k? sysref? avdd1_sr 1k? 20k? 20k? level translator v cm = 0.85v 1 1752-013 figure 106 . sysref inputs drvdd drgnd drvdd drgnd output driver emphasis/swing control (spi) data+ data? serdoutx+ x = 0, 1, 2, 3 serdoutx? x = 0, 1, 2, 3 1 1752-014 figure 107 . digital outputs 20k? 20k? level translator v cm = 0.85v syncinb pin control (spi) syncinb+ dvdd 1k? dgnd syncinb? dvdd 1k? dgnd v cm 1 1752-015 figure 108 . syncinb inputs 30k spivdd esd protected esd protected 1k? spivdd sclk 1 1752-016 figure 109 . sclk input
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 34 of 97 30k esd protected esd protected 1k? spivdd csb 1 1752-017 figure 110 . csb input 30k esd protected esd protected 1k? spivdd spivdd sdi sdio sdo 1 1752-018 figure 111 . sdio input esd protected esd protected spivdd fd_a/fd_b fd jesd lmfc fd_x pin control (spi) jesd sync~ temperature diode (fd_a only) 1 1752-019 figure 112 . fd_a/fd_b outputs esd protected esd protected 1k? spivdd pdwn/ stby pdwn control (spi) 1 1752-020 figure 113 . pdwn/stby input esd protected esd protected v_1p0 v_1p0 pin control (spi) avdd2 1 1752-021 figure 114 . v_1p0 input/output
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 35 of 97 theory of operation the ad9680 has two analog input channels and four jesd204b output lane pairs. the adc is designed to sampl e wide bandwidth analog signals of up to 2 ghz. the ad9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. the dual adc cores feat ure a multistage, differential pipelined architecture with integrated output error correction logic. each adc features wide bandwidth inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. the ad9680 has several functions that simplify the agc function in a communications receiver. the programmable threshold detector allows monitoring of the incoming signal power using the fast dete ct output bits of the adc. if the input signal level exceeds the programmable threshold, the fast detect indicator goes high. because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition a t the adc input. the subclass 1 jesd204b - based high speed serialized output data lanes can be configured in one - lane (l = 1), two - lane (l = 2), and four - lane (l = 4) configurations, depending on the sample rate and the decimation ratio. multiple device syn chronization is supported through the sysref and syncinb input pins. adc architecture the architecture of the ad9680 consists of an input buffered pipelined adc. the input buffer is designed to provide a termination impedance to the analog input signal. this termination impedance can be changed using the spi to meet the termination needs of the driver/amplifier. the def ault termination value is set to 400 . the equivalent circuit diagram of the analog input termination is shown in figure 104 . the input buffer is optimized for high linearity, low noise, and low power. the input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the adc. the buffer is optimized for high linearity, low noise, and low power. the quantized outputs from each stage are combined into a final 14- bit result in the digital correction logic. the pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. sampling occurs on th e rising edge of the clock. analog input conside rations the analog input to the ad9680 is a differential buffer. the internal common - mode voltage of the buffer is 2.05 v. the clock signal alternat ely switches the input circuit between sample mode and hold mode. when the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one - half of a clock cycle. a small resistor, in s eries with each input, can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the anal og inputs and, thus, achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a differential capacitor or two single - ended capacitors can be place d on the inputs to provide a matching passive network. this ultimately creates a low - pass filter at the input, which limits unwanted broadband noise. for more information, refer to the an - 742 appl ication note , the an - 827 application note , and the analog dialogue article transforme r - coupled front - end for wideband a/d converters (volume 39, april 2005). in general, the precise values depend on the application. for best dynamic performance, the source impedances driving vin+x and vin?x must be matched such that common - mode settling e rrors are symmetrical. these errors are reduced by the common - mode rejection of the adc. an internal reference buffer creates a differential reference that defines the span of the adc core. maximum snr performance is achieved by setting the adc to the larg est span in a differentia l configuration. in the case of the ad9680 , the available span is programmable through the spi port from 1.46 v p - p to 2.06 v p - p differential, with 1.58 v p - p differential being the default for the ad9680 - 1250, 1.70 v p - p differential being the default for the ad9680 - 1000 and ad9680 - 820 , and 2.06 v p - p differential being the default for the ad9680 - 500. differential input configurations there are several ways to drive the ad9680 , either actively or passively. however, optimum performance is achieved by driving the analog input differentially. for applications where snr and sfdr are key parameters, differential transfo rmer coupling is the recommended input configuration (see figure 115 and table 9 ) because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9680 . for low to midrange frequencies, a double balun or double transformer network (see figure 115 and table 9 ) is recom - mended for optimum performance of the ad9680 . for higher frequencies in the second or third nyquist zones, it is better to remove some of the front - end passive components to ensure wideband operation (see figure 115 and table 9 ).
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 36 of 97 adc r1 r2 r1 0.1f 0.1f 0.1f c2 r3 r3 balun notes 1. see t able 9 for component v alues. r2 c1 c1 1 1752-168 figure 115 . differential transformer - coupled configuration for ad9680 table 9 . differential transformer - coupled input configuration component values device frequency range transforme r r1 ( ) r2 ( ) r3 ( ) c1 (pf) c2 (pf) ad9680 - 500 dc to 250 mhz etc1 -1 -13 10 50 10 4 2 250 mhz to 2 ghz bal - 0006/bal - 0006smg 10 50 10 4 2 ad9680 - 820 dc to 410 mhz etc1 -1 -13 10 50 10 4 2 410 mhz to 2 ghz bal - 0006/bal - 0006smg 10 50 10 4 2 ad9680 - 1000 dc to 500 mhz etc1 -1 - 13/bal - 0006smg 25 25 10 4 2 500 mhz to 2 ghz bal - 0006/bal - 0006smg 25 25 0 open open ad9680 - 1250 dc to 625 mhz bal - 0006smg 10 50 15 4 2 625 mhz to 2 ghz bal - 0006smg 10 50 0 open open input common mode the analog inputs of the ad9680 are internally biased to the common mode as shown in figure 116 . the common - mode buffer has a limited range in that the performance suffers greatly if the common - mode voltage drops by more than 100 mv. therefore, in dc - coupled applications, set the common - mode voltage to 2.05 v, 100 mv to ensure proper adc operation. the full - scale voltage setting must be at a 1.7 v p - p differential if running in a dc - coupled application. analog input buffer controls a nd sfdr optimization the ad9680 input buffer offers flexible controls for the analog inputs, such as input termination, buffer current, and input full - scale adjustment. all the available controls are shown in figure 116 . 10pf vin+x vin?x avdd3 avdd3 avdd3 v cm buffer 400 200 200 67 28 200 200 67 28 avdd3 avdd3 1.5pf 3pf 1.5pf 3pf ain control spi registers (0x008, 0x015, 0x016, 0x018, 0x019, 0x01a, 0x 1 1a, 0x934, 0x935) 1 1752-169 figure 116 . analog input controls using the 0x018, 0x019, 0x01a, 0x11a, 0x934, and 0x935 registers , the buffer behavior on each channel can be adjusted to optimize the sfdr over various input frequencies and bandwidths of interest. input buffer control registers (0x018, 0x019, 0x01a, 0x935, 0x934, 0x11a) the input buffer has many registers that set the bias currents and other settings for operation at different frequencies. these bias currents and settings can be changed to suit the input frequency range of operation. register 0x018 controls the buffer bias current to help with the kickback from the adc core. this setting can be scaled from a low setting of 1.0 to a high setting of 8.5. the default setting is 3.0 for the ad9680 - 1000 and ad9680 - 820, and 2.0 for the ad9680 - 500 . these settings are sufficient for operation in the first nyquist zone for the products. when the input buffer current in register 0x018 is set, the amount of current required by the avdd3 supply changes. this relationship is shown in figure 117 . for a complete list of buffer current settings, see table 36. i avdd3 (ma) buffer control 1 setting 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 11752-341 50 100 150 200 250 300 ad9680-1250, ad9680-1000, and ad9680-820 ad9680-500 figure 117 . i avdd3 vs . buffer control 1 setting in register 0x018
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 37 of 97 the 0x019, 0x01a, 0x11a, and 0x935 registers offer secondary bias controls for the input buffer for frequencies >500 mhz. register 0x934 can be used to reduce input capacitance to achieve wider signal bandwidth but may result in slightly lower linearity and noise performance. these register settings do not impact the avdd3 power as much as register 0x018 does. for frequencies <500 mhz, it is recommended to use the default settings for these registers. table 10 shows the recommended values for the buffer current control registers for various speed grades. register 0x11a is used when sampling in higher nyquist zones (>500 mhz for the ad9680 - 1000 ). this setting enables the adc sampling network to optimize the sampling and settling times internal to the adc for high frequency operation. for frequencies greater than 500 mhz, it is recommended t o operate the adc core at a 1.46 v full - scale setting irrespective of the speed grade. this setting offers better sfdr without any significant penalty in snr. figure 118, figure 119 , and figure 120 show the sfdr vs. analog input frequency for various buffer settings for the ad9680 - 1250 . the recommended settings shown in table 10 were used to take the data while changing the contents of register 0x018 only. 60 65 70 75 80 85 sfdr (dbfs) input frequency (mhz) 10.3 147.3 212.3 290.3 355.3 433.3 511.3 589.3 667.3 250mhz 350mhz 450mhz 550mhz 1 1752-631 figure 118 . buffer current sweeps, ad9680 - 1250 (sfdr vs. i buff ); f in < 500 mhz; front - end network shown in figure 115 55 60 65 70 75 80 sfdr (dbfs) input frequency (mhz) 602.3 680.3 758.3 836.3 914.3 992.3 1070.3 1148.3 1226.3 350mhz 450mhz 550mhz 650mhz 1 1752-632 figure 119 . buffer current sweeps, ad9680 - 1250 (sfdr vs. i buff ); 600 mhz < f in < 1300 mhz; front - end network shown in figure 115 58 60 64 68 72 62 66 70 74 76 sfdr (dbfs) input frequency (mhz) 650mhz 750mhz 850mhz 1304.3 1408.3 1512.3 1616.3 1720.3 1824.3 1928.3 1 1752-633 figure 120 . buffer current sweeps, ad9680 - 1250 (sfdr vs. i buff ); 1300 mhz < f in < 2000 mhz; front - end network shown in figure 115 figure 121, figure 122 , and figure 123 show the sfdr vs. analog input frequency for various buffer settings for the ad9680 - 1000 . the recommended settings shown in table 10 were used to take the data while changing the contents of register 0x018 only. 50 55 60 65 70 75 80 85 90 10 60 1 10 160 210 260 310 360 410 460 sfdr (dbfs) analog input frequenc y (mhz) 1.5 3.0 4.5 1 1752-170 figure 121 . buffer current sweeps, ad9680 - 1000 (sfdr vs. i buff ); f in < 500 mhz; front - end network shown in figure 115 40 45 50 55 60 65 70 75 80 85 sfdr (dbfs) analog input frequenc y (mhz) 503.4 677.6 851.9 1026.2 1200.5 1374.8 4.0 5.0 6.0 1 1752-172 figure 122 . buffer current sweeps, ad9680 - 1000 (sfdr vs. i buff ); 500 mhz < f in < 1500 mhz; front - end ne twork shown in figure 115
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 38 of 97 40 45 50 55 60 65 70 75 80 sfdr (dbfs) analog input frequenc y (mhz) 1513.4 1607.4 1701.5 1795.6 1889.8 4.5 5.5 6.5 7.5 8.5 1 1752-173 figure 123 . buffer current sweeps, ad9 680- 1000 (sfdr vs. i buff ); 1500 mhz < f in < 2000 mhz; front - end network shown in figure 115 in certain high frequency applications, the sfdr can be improved by reducing the full - scale setting, as shown in table 10 . at high frequencies, the performance of the adc core is limited by jitter . the sfdr can be improved by backi ng off of the full scale level. figure 124 shows the sfdr and snr vs. full - scale input level at different high frequencies for the ad9680 - 1000. 1.52ghz 1.65ghz 1.76ghz 1.9ghz 1.95ghz 55 60 65 70 75 80 55 60 65 70 75 80 ?3 ?2 ?1 sfdr (dbfs) snr (dbc) input leve l (dbfs) 1 1752-174 1.52ghz 1.65ghz 1.76ghz 1.9ghz 1.95ghz figure 124 . snr/sfdr vs. analog input level vs. input frequencies, ad9680 - 1000 figure 125, figure 126 , and figure 127 show the sfdr vs. analog input frequency for various buffer settings for the ad9680 - 820 . the re commended settings shown in table 10 were used to take the data while changing the contents of register 0x018 only. 1 1752-523 sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 80 85 90 95 10.3 65.5 95.3 125.4 150.3 170.3 180.3 210.5 240.3 270.3 301.3 330.3 340.7 360.3 390.3 420.3 450.3 1.5 2.0 3.0 4.5 figure 125 . buffer current sweeps, ad9680 - 820 (sfdr vs. i buff ); f in < 500 mhz; front - end network shown in figure 115 1 1752-524 sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 80 85 420.3 450.3 480.3 510.3 515.3 610.3 766.3 810.3 985.3 1022.3 3.5 4.5 5.5 6.5 7.5 figure 126 . buffer current sweeps, ad9680 - 820 (sfdr vs. i buff ); 500 mhz < f in < 1000 mhz; front - end network shown in figure 115 1 1752-525 sfdr (dbfs) analog input frequency (mhz) 50 55 60 65 70 75 80 1022.3 1110.3 1205.3 1315.3 1420.3 1510.3 1600.3 1720.3 1810.3 1920.3 1950.3 6.5 7.5 8.5 figure 127 . buffer current sweeps, ad9680 - 820 (sfdr vs. i buff ); 1000 mhz < f in < 2000 mhz; front - end network shown in figure 115
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 39 of 97 figure 128 , figure 129 , and figure 130 show the sfdr vs. analog input frequency for various buffer settings for the ad9680 - 500 . the recommended settings shown in table 10 were used to take the data while changing the contents of register 0x018 only. 30 40 50 60 70 80 90 100 10.3 95.3 150.3 180.3 240.3 301.3 340.7 390.3 450.3 sfdr (dbfs) analog input frequenc y (mhz) 1.0 1.5 2.0 3.0 4.5 1 1752-145 figure 128 . buffer current sweeps, ad9680 - 500 ( sfdr vs. i buff ); f in < 500 mhz; front - end network shown in figure 115 buffer control 1 (0x018) = 1.0, 1.5, 2.0, 3.0, or 4.5 65 70 75 80 85 90 95 450.3 480.3 510.3 515.3 analog input frequenc y (mhz) 610.3 765.3 810.3 985.3 sfdr (dbfs) 4.0 5.0 6.0 7.0 8.0 1 1752-175 figure 129 . buffer current sweeps, ad9680 - 500 (sfdr vs. i buff ); 450 mhz < f in < 1000 mhz; front - end network shown in figure 115 sfdr (dbfs) 40 45 50 55 60 65 70 75 80 1010.3 1205.3 1410.3 1600.3 1810.3 1950.3 analog input frequenc y (mhz) 4.0 5.0 6.0 7.0 8.0 1 1752-176 figure 130 . buffer current sweeps, ad9680 - 500 (sfdr vs. i buff ); 1 ghz < f in < 2 ghz; front - end network shown in figure 115
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 40 of 97 table 10 . recommended register settings for sfdr optimization at different input frequencies product frequency buffer control 1 (0x 018) buffer current control buffer control 2 (0x019) buffer bias setting buffer control 3 (0x01a) buffer bias setting buffer control 4 (0x11a) high frequency setting buffer control 5 (0x935) low frequency setting input full - scale range (0x025) input full - s cale control (0x030) input termination (0x016) 1 input capacitance (0x934) ad9680 - 500 dc to 250 mhz 0x20 (2.0) 0x60 (setting 3) 0x0a (setting 3) 0x00 (off) 0x04 (on) 0x0c (2.06 v p - p) 0x04 0x0c/0x1c/ 0x1f 250 mhz to 500 mhz 0x70 (4.5) 0x60 (setting 3) 0x0a (setting 3) 0x00 (off) 0x04 (on) 0x0c (2.06 v p - p) 0x04 0x0c/0x1c/ 0x1f 500 mhz to 1 ghz 0x80 (5.0) 0x40 (setting 1) 0x08 (setting 1) 0x00 (off) 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0c/0x1c/ 0x1f or 0x00 2 1 ghz to 2 ghz 0xf0 (8.5) 0x40 (setting 1) 0x08 (setting 1) 0x00 (off) 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0c/0x1c/ 0x1f or 0x00 1 ad9680 - 820 dc to 200 mhz 0x10 (1.5) 0x40 (setting 1) 0x09 (setting 2) 0x00 (off) 0x04 (on) 0x0a (1.70 v p - p) 0x14 0x0c/0x1c/ 0x1f dc to 410 mhz 0x40 (3.0) 0x40 (setting 1) 0x09 (setting 2) 0x00 (off) 0x04 (on) 0x0a (1.70 v p - p) 0x14 0x0c/0x1c/ 0x1f 500 mhz to 1 ghz 0x80 (5.0) 0x40 (setting 1) 0x08 (setting 1) 0x00 (off) 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0c/0x1c/ 0x1f or 0x00 2 1 ghz to 2 ghz 0xf0 (8.5) 0x40 (setting 1) 0x08 (setting 1) 0x00 (off) 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0c/0x1c/ 0x1f or 0x00 1 ad9680 - 1000 dc to 150 mhz 0x10 (1.5) 0x50 (setting 2) 0x09 (setting 2) 0x00 (off) 0x04 (on) 0x0a (1.70 v p - p) 0x18 0x0e/0x1e/ 0x1f dc to 500 mhz 0x40 (3.0) 0x50 (setting 2) 0x09 (setting 2) 0x00 (off) 0x04 (on) 0x0a (1.70 v p - p) 0x18 0x0e/0x1e/ 0x1f 500 mhz to 1 ghz 0xa0 (6.0) 0x60 (setting 3) 0x09 (setting 2) 0x20 (on) 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0e/0x1e/ 0x1f or 0x00 1 1 ghz to 2 ghz 0xd0 (7.5) 0x70 (setting 4) 0x09 (setting 2) 0x20 (on) 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0e/0x1e/ 0x1f or 0x00 1 ad9680 - 1250 dc to 625 mhz 0x50 (3.5) 0x50 (setting 2) 0x09 (setting 2) 0x00 (off) 0x04 (on) 0x0a (1.58 v p - p) 0x18 0x0e/0x1e/ 0x1f >625 mhz 0xa0 (6.0) 0x50 (setting 2) 0x09 (setting 2) n/a 3 0x00 (off) 0x08 (1.46 v p - p) 0x18 0x0e/0x1e/ 0x1f or 0x00 1 1 the input termination can be changed to accommodate the application with little or no impact to ac performance. 2 the input capacitance can be set to 1.5 pf to achieve wider input bandwidth but result s in slightly lower ac performance. 3 n/a means not applicable.
pr o duct overview o nline documentation design resources discussion sample & buy data sheet ad9680 rev. c | page 41 of 97 absolute maximum input swing the absolute maximum input swing allowed at the inputs of the ad9680 is 4.3 v p-p differential. signals operating near or at this level can cause permanent damage to the adc. voltage reference a stable and accurate 1.0 v voltage reference is built into the ad9680 . this internal 1.0 v reference is used to set the full- scale input range of the adc. the full-scale input range can be adjusted via the adc function register 0x025. for more information on adjusting the input swing, see table 36. figure 131 shows the block diagram of the internal 1.0 v reference controls. adc core full-scale voltage adjust v_1p0 pin control spi register (0x025, 0x02, and 0x024) v_1p0 vin?a/ vin?b vin+a/ vin+b internal v_1p0 generator input full-scale range adjust spi register (0x025, 0x02, and 0x024) 11752-031 figure 131. internal reference configuration and controls the spi register 0x024 enables the user to either use this internal 1.0 v reference, or to provide an external 1.0 v reference. when using an external voltage reference, provide a 1.0 v reference. the full-scale adjustment is made using the spi, irrespective of the reference voltage. for more information on adjusting the full-scale level of the ad9680 , refer to the memory map register table s e c t ion. the use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the adc or to improve thermal drift characteristics. figure 132 shows the typical drift characteristics of the internal 1.0 v reference. ?50 0 25 90 v_1p0 voltage (v) temperature (c) 0.9998 0.9999 1.0000 1.0001 1.0002 1.0003 1.0004 1.0005 1.0006 1.0007 1.0008 1.0009 1.0010 11752-106 figure 132. typical v_1p0 drift the external reference must be a stable 1.0 v reference. the adr130 is a good option for providing the 1.0 v reference. figure 133 shows how the adr130 can be used to provide the external 1.0 v reference to the ad9680 . the grayed out areas show unused blocks within the ad9680 while using the adr130 to provide the external reference. full-scale voltage adjust v_1p0 0.1f v out 4 set 5 nc 6 v in 3 gnd 2 nc 1 adr130 0.1f input full-scale control internal v_1p0 generator 11752-032 figure 133. external reference using adr130
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 42 of 97 clock input consider ations for optimum performance, drive the ad9680 s ample clock inputs (clk+ and clk?) with a differential signal. this signal is typically ac - coupled to the clk+ and clk? pins via a transformer or clock drivers. these pins are biased internally and require no additional biasing. figure 134 shows a preferred method for clocking the ad9680 . the low jitter clock source is converted from a single - ended signal to a differential signal using an rf transformer. adc clk+ clk? 0.1f 0.1f 100? 50? clock input 1:1z 1 1752-035 figure 134 . transformer - coupled differential clock another option is to ac couple a differential cml or lvds signal to the sample clock input pins, as shown in figure 135 and figure 136. adc clk+ clk? 0.1f 0.1f z0 = 50 z0 = 50 33? 33? 71? 10pf 3.3v 1 1752-036 figure 135 . differential cm l sample clock adc clk+ clk? 0.1f 0.1f 0.1f 0.1f 50? 1 50? 1 100? clock input lvds driver clk+ clk? 1 50 resistors are optional. clock input 1 1752-037 figure 136 . differential lvds sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance charac teristics. in applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. the ad9680 can be clocked at 2 ghz with the i nternal clock divider set to 2. the output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal adc. see the memory map sec tion for more details on using this feature. input clock divider the ad9680 contains an input clock divider with the ability to divide the nyquist input clock by 1, 2, 4, and 8. the divider ratio s can be selected using register 0x10b. this is shown in figure 137. the maximum frequency at the clk inputs is 4 ghz. this is the limit of the divider. in applicatio ns where the clock input is a multiple of the sample clock, care must be taken to program the appropriate divider ratio into the clock divider before applying the clock signal. this ensures that the current transients during device startup are controlled. clk+ clk? 2 4 reg 0x10b 8 1 1752-038 figure 137 . clock divider circuit the ad9680 clock divider can be synchronized using the external sysref input. a valid sysref causes the clock divider to reset to a p rogrammable state. this synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. see the multichip synchronization section for more information. input clock divider ? period delay adjust the input clock divider inside the ad9680 provides phase delay in increments of ? the input clock cycle. register 0x10c can be programmed to enable this delay independently for each channel. changing this register does not affect the stability of the jesd204b link. clock fine delay adjust the ad9680 sampling edge instant can be adjusted by writing to register 0x117 and register 0x118. setting bit 0 of register 0x117 enables the feature, and bits[7:0] of register 0x118 set the value of the delay. this value can be programmed individually for each channel. the clock delay can be adjusted from ?151.7 ps to +150 ps in ~1.7 ps increments. the clock delay adjust takes effect immediately when it is enabled via spi writes. enabling the clock fine delay adjust in register 0x117 causes a datapath reset. however, the contents of register 0x118 can be changed without affecting the stability of the jesd204b link. clock jitter considerations high speed, high resolution adcs are sensitive to the quality o f the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by snr = 20 log 10 (2 f a t j ) in this equation, the rms aperture jitter represents the root mean square of all jitter sour ces, including the clock input, analog input signal, and adc aperture jitter specifications.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 43 of 97 if undersampling applications are particularly sensitive to jitter (see figure 138). 1 1752-039 130 120 110 100 90 80 70 60 50 40 30 10 100 1000 10000 snr (db) analog input frequency (mhz) 12.5 f s 25 f s 50 f s 100 f s 200 f s 400 f s 800 f s figure 138 . ideal snr vs. input frequency and jitter treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9680 . separate power supplies for clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. if the clock is generated from another type of source ( by gating, dividing, or other methods), retime the clock by the original clock at the last step. refer to the an - 501 application note and the an - 756 application note for more in - depth information about jitter performance as it relates to adcs. figure 139 shows the estimated snr of the ad9680 - 1000 across input frequency for different clock induced jitter values. the snr can be estimated by using the following equation: ? ? ? ? ? ? ? ? + = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 10 10 10 10 10log (dbfs) jitter adc snr snr snr 1 1752-526 snr (dbfs) input frequency (mhz) 45 50 55 60 65 70 10 100 1k 10k 25f s 50f s 75f s 100f s 125f s 150f s 175f s 200f s figure 139 . estimated snr degradation for the ad9680 - 1000 vs. input frequency and rms jitter power - down/standby mode the ad9680 has a pdwn/stby pin that can be used to configure the device in power - down or standby mode. the default operation is pdwn. the pdwn/stby pin is a logic high pin. when in power - down mode, the jesd204b link is disrupted. the power - down option can also be se t via register 0x03f and register 0x040. in standby mode, the jesd204b link is not disrupted and transmits zeros for all converter samples. this can be changed using register 0x571, bit 7 to select /k/ characters. temperature diode the ad9680 contains a diode - based temperature sensor for measuring the temperature of the die. this diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. the tempera ture diode voltage can be output to the fd_a pin using the spi. use register 0x028, bit 0 to enable or disable the diode. register 0x028 is a local register. channel a must be selected in the device index register (0x008) to enable the temperature diode re adout. configure the fd_a pin to output the diode voltage by programming register 0x040[2:0]. see table 36 for more information. the voltage response of the temperatu re diode (spivdd = 1.8 v) is shown in figure 140. diode voltage (v) temperature (c) 0.60 0.65 0.70 0.75 0.80 0.85 0.90 11752-353 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 105 115 125 figure 140 . temperature diode voltage vs. temperature
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 44 of 97 adc overrange and fa st detect in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overrange bit in the jesd204b outputs provides information on the state of the analog input that is of limited usefulness. therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. in additi on, because input signals can have significant slew rates, the latency of this function is of major concern. highly pipelined converters can have significant latency. the ad9680 contains fast dete ct circuitry for individual channels to monitor the threshold and assert the fd_a and fd_b pins. adc overrange the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange indicator can be embedded within the jesd204b link as a control bit (when csb > 0). the latency of this overrange indicator matches the sample latency. the ad9680 also records any overrange condition in any of the eight virtual conv erters. for more information on the virtual converters, refer to figure 146 . the overrange status of each virtual converter is registered as a sticky bit in register 0x563. the contents of register 0x563 can be cleared using register 0x562, by toggling the bits corre sponding to the virtual converter to set and reset position. fast threshold detec tion (fd_a and fd_b) the fd bit is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. the fd bit is only cleared w hen the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. this feature provides hysteresis and prevents the fd bit from excessively toggling. the operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in figure 141. the fd indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at register 0x247 and register 0x248. the selected threshold register is compared with the signal magnitude at the output of the adc. the fast upper threshol d detection has a latency of 28 clock cycles (maximum). the approximate upper threshold magnitude is defined by upper threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 13 ) the fd indicators are not cleared until the signal drops below the lower th reshold for the programmed dwell time. the lower threshold is programmed in the fast detect lower threshold registers, located at register 0x249 and register 0x24a. the fast detect lower threshold register is a 13 - bit register that is compared with the sig nal magnitude at the output of the adc. this comparison is subject to the adc pipeline latency, but is accurate in terms of converter resolution. the lower threshold magnitude is defined by lower threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 1 3 ) for example, to set an upper threshold of ?6 dbfs, write 0xfff to register 0x247 and register 0x248. to set a lower threshold of ?10 dbfs, write 0xa1d to register 0x249 and register 0x24a. the dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at register 0x24b and register 0x24c. see the memory map section (register 0x040, and register 0x245 to register 0x24c in table 36 ) for more details. upper threshold lower threshold fd_a or fd_b midscale dwell time timer reset by rise above lower threshold timer completes before signal rises above lower threshold dwell time 1 1752-040 figure 141 . threshold settings for fd_a and fd_b signals
pr o duct overview o nline documentation design resources discussion sample & buy data sheet ad9680 rev. c | page 45 of 97 signal monitor the signal monitor block provides additional information about the signal being digitized by the adc. the signal monitor computes the peak magnitude of the digitized signal. this information can be used to drive an agc loop to optimize the range of the adc in the presence of real-world signals. the results of the signal monitor block can be obtained either by reading back the internal values from the spi port or by embedding the signal monitoring information into the jesd204b interface as special control bits. a global, 24-bit programmable period controls the duration of the measurement. figure 142 shows the simplified block diagram of the signal monitor block. from memory map down counter is count = 1? magnitude storage register from input signal monitor holding register load clear compare a > b load load to sport over jesd204b and memory map signal monitor period register (smpr) 0x271, 0x272, 0x273 11752-087 figure 142. signal monitor block the peak detector captures the largest signal within the observation period. the detector only observes the magnitude of the signal. the resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. the peak magnitude can be derived by using the following equation: peak magnitude (dbfs) = 20log( peak detector value /2 13 ) the magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (smpr). the peak detector function is enabled by setting bit 1 of register 0x270 in the signal monitor control register. the 24-bit smpr must be programmed before activating this mode. after enabling peak detection mode, the value in the smpr is loaded into a monitor period timer, which decrements at the decimated clock rate. the magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. the initial value of the magnitude storage register is set to the current adc input signal magnitude. this comparison continues until the monitor period timer reaches a count of 1. when the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the sport over the jesd204b interface. the monitor period timer is reloaded with the value in the smpr, and the countdown restarts. in addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 46 of 97 sport over jesd204b the signal moni tor data can also be serialized and sent over the jesd204b interface as control bits. these control bits must be deserialized from the samples to reconstruct the statistical data. the signal control monitor function is enabled by setting bits[1:0] of regis ter 0x279 and bit 1 of register 0x27a. figure 143 shows two different example configurations for the signal monitor control bit locations inside the jesd204b samples. a maximum of three control bits can be inserted into the jesd204b samples; however, only one control bit is required for the signal monito r. control bits are inserted from msb to lsb. if only one control bit is to be inserted (cs = 1), only the most significant control bit is used (see example configuration 1 and example configuration 2 in figure 143 ). to select the sport over jesd204b option, program register 0x559, register 0x55a, and register 0x58f. see table 36 for more information on setting these bits. figure 144 shows the 25 - bit frame data that encapsulates the peak detector v alue. the frame data is transmitted msb first with five 5 - bit subframes. each subframe contains a start bit that can be used by a receiver to validate the deserialized data. figure 145 shows the sport over jesd204b signal monitor data with a monitor period timer set to 80 samples. 15 14-bit converter resolution (n = 14) tail x 1 control bit (cs = 1) 1-bit control bit (cs = 1) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 tail bit serialized signal monitor frame data example configuration 1 (n' = 16, n = 15, cs = 1) example configuration 2 (n' = 16, n = 14, cs = 1) serialized signal monitor frame data 16-bit jesd204b sample size (n' = 16) s[13] x s[12] x s[11] x s[10] x s[9] x s[8] x s[7] x s[6] x s[5] x s[4] x s[3] x s[2] x s[1] x s[0] x ctrl [bit 2] x ctrl [bit 2] x s[14] x s[13] x s[12] x s[11] x s[10] x s[9] x s[8] x s[7] x s[6] x s[5] x s[4] x s[3] x s[2] x s[1] x s[0] x 15-bit converter resolution (n = 15) 16-bit jesd204b sample size (n' = 16) 1 1752-088 figure 143 . signal monitor control bit locations 25-bit frame 5-bit idle sub-frame (optional) 5-bit identifier sub-frame 5-bit data msb sub-frame 5-bit data sub-frame 5-bit data sub-frame 5-bit data lsb sub-frame 5-bit sub-frames p[] = peak magnitude value idle 1 idle 1 idle 1 idle 1 idle 1 start 0 p[0] 0 0 0 start 0 p[4] p[3] p[2] p1] start 0 p[8] p[7] p[6] p5] start 0 p[12] p[11] p[10] p[9] start 0 id[3] 0 id[2] 0 id[1] 0 id[0] 1 1 1752-089 figure 144 . sport over jesd204b signal monitor frame data
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 47 of 97 payload #3 25-bit frame (n) payload #3 25-bit frame (n + 1) payload #3 25-bit frame (n + 2) idle idle idle idle idle idle idle idle idle idle idle ident. data msb data data data lsb idle idle idle idle idle idle idle idle idle idle idle ident. data msb data data data lsb idle idle idle idle idle idle idle idle idle idle idle ident. data msb data data data lsb smpr = 80 samples (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00) 80 sample period 80 sample period 80 sample period 1 1752-090 figure 145 . sport over jesd204b signal monitor example with period = 80 samples
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 48 of 97 digital downconverte r (ddc) the ad9680 includes four digital downconverters (ddc 0 to ddc 3) that provide filtering and reduce the output data rate. this digital processing section includes an nco, a half - band decimating filter, a n fir filter, a gain stage, and a complex - real conversion stage. each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. the digital downconverter can be configure d to output either real data or complex output data. the ddcs output a 16 - bit stream. to enable this operation, the converter number of bits, n, is set to a default value of 16, even though the analog core only outputs 14 bits. in full bandwidth operation, the adc outputs are the 14 - bit word followed by two zeros, unless the tail bits are enabled. ddc i/q input select ion the ad9680 has two adc channels and four ddc channels. each ddc channel has tw o input ports that can be paired to support both real or complex inputs through the i/q crossbar mux. for real signals, both ddc input ports must select the same adc channel (for example, ddc input port i = adc channel a, and input port q = adc channel a). for complex signals, each ddc input port must select different adc channels (for example, ddc input port i = adc channel a, and input port q = adc channel b). the inputs to each ddc are controlled by the ddc input selection registers (register 0x311, regi ster 0x331, register 0x351, and register 0x371). see table 36 for information on how to configure the ddcs. ddc i/q output selec tion each ddc channel has two output ports that can be paired to support both real or complex outputs. for real output signals, only the ddc output port i is used (the ddc output port q is invalid). for complex i/q output signals, both ddc output port i and ddc output port q are used. the i/q outputs to each ddc channel are controlled by the ddc complex to real enable bit (bit 3) in the ddc control registers (register 0x310, register 0x330, register 0x350, and register 0x370). the chip q ignore bit (bit 5) in the chip application mode register (register 0x200) controls the chip output muxing of all the ddc channels. when all ddc channels use real outputs, this bit must be set high to ignore all ddc q output ports. when any of the ddc channels are set to use complex i/q outputs, the user must cl ear this bit to use both ddc output port i and ddc output port q. for more information, see figure 154. ddc general descript ion the four ddc blocks are used to extrac t a portion of the full digital spectrum captured by the adc(s). they are intended for if sampling or oversampled baseband radios requiring wide bandwidth input signals. each ddc block contains the fol lowing signal processing stages. frequency translation stage (optional) the frequency translation stage consists of a 12 - bit complex nco and quadrature mixers that can be used for frequency translation of both real or complex input signals. this stage shifts a portion of the available digital spectrum down to baseband. filtering stage after shifting down to baseband, the filtering stage decimates the frequency spectrum using a chain of up to four half - b and low - pass filters for rate conversion. the decimation process lowers the output data rate, which in turn reduces the output interface rate. gain stage (optional) due to losses associated with mixing a real input signal down to baseband, the gain stage c ompensates by adding an additional 0 db or 6 db of gain. complex to real conversion stage (optional) when real outputs are necessary, the complex to real conversion stage converts the complex outputs back to real by performing an f s /4 mixing operation plus a filter to remove the complex component of the signal. figure 146 shows the detailed block diagram of the ddcs implemented in the ad9680 .
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 49 of 97 nco + mixer (optional) complex to real conversion (optional) hb4 fir dcm = bypass or 2 hb3 fir dcm = bypass or 2 hb2 fir dcm = bypass or 2 hb1 fir dcm = 2 gain = 0db or 6db ddc 3 sysref real/i real/q real/i converter 6 q converter 7 i q nco + mixer (optional) complex to real conversion (optional) hb4 fir dcm = bypass or 2 hb3 fir dcm = bypass or 2 hb2 fir dcm = bypass or 2 hb1 fir dcm = 2 gain = 0db or 6db ddc 0 sysref real/i real/q real/i converter 0 q converter 1 i q nco + mixer (optional) complex to real conversion (optional) hb4 fir dcm = bypass or 2 hb3 fir dcm = bypass or 2 hb2 fir dcm = bypass or 2 hb1 fir dcm = 2 gain = 0db or 6db ddc 1 sysref real/i real/q real/i converter 2 q converter 3 i q nco + mixer (optional) complex to real conversion (optional) hb4 fir dcm = bypass or 2 hb3 fir dcm = bypass or 2 hb2 fir dcm = bypass or 2 hb1 fir dcm = 2 gain = 0db or 6db ddc 2 sysref real/i real/q real/i converter 4 q converter 5 i q output interface i/q crossbar mux adc sampling at f s real/i adc sampling at f s real/i synchronization control circuits sysref 1 1752-041 figure 146 . ddc detailed block diagram figure 147 shows an example usage of one of the four ddc blocks with a real input signal and four half - band filters (hb4, hb3, hb2, an d hb1). it shows both complex (decimate by 16) and real (decimate by 8) output options. when ddcs have different decimation ratios, the chip decimation ratio (register 0x201) must be set to the lowest decimation ratio of all the ddc blocks. in this scenari o, samples of higher decimation ratio ddcs are repeated to match the chip decimation ratio sample rate. whenever the nco frequency is set or changed, the ddc soft reset must be issued. if the ddc soft reset is not issued, the output may potentially show am plitude variations. table 11, table 12, table 13, table 14 , and table 15 show the ddc samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 50 of 97 cos(t) 0 90 i q real bandwidth of interest bandwidth of interest image digital filter response dc dc adc sampling at f s real real half- band filter hb4 fir 2 half- band filter hb3 fir 2 half- band filter hb2 fir 2 half- band filter hb1 fir i i half- band filter hb4 fir 2 half- band filter hb3 fir 2 half- band filter hb2 fir 2 2 2 half- band filter hb1 fir q q adc real input?sampled at f s filtering stage 4 digital half-band filters (hb4 + hb3 + hb2 + hb1) frequency translation stage (optional) digital mixer + nco for f s /3 tuning, the frequency tuning word = round (( f s /3)/ f s 4096) = +1365 (0x555) nco tunes center of bandwidth of interest to baseband bandwidth of interest image (?6db loss due to nco + mixer) bandwidth of interest (?6db loss due to nco + mixer) ? f s /2 ? f s /3 ? f s /4 ? f s /8 f s /16 f s /8 f s /4 f s /3 f s /2 ? f s /16 ? f s /32 f s /32 ? f s /2 ? f s /3 ? f s /4 ? f s /8 f s /16 f s /8 f s /4 f s /3 f s /2 ? f s /16 ? f s /32 f s /32 Csin(t) 12-bit nco dc digital filter response dc dc i q i q 2 2 i q real/i complex to real i q gain stage (optional) 0db or 6db gain complex (i/q) outputs decimate by 16 gain stage (optional) 0db or 6db gain real (i) outputs decimate by 8 complex to real conversion stage (optional) f s /4 mixing + complex filter to remove q ? f s /8 f s /16 f s /8 ? f s /16 ? f s /32 f s /32 ? f s /8 f s /16 f s /8 ? f s /16 ? f s /32 f s /32 f s /16 ? f s /16 ? f s /32 f s /32 6db gain to compensate for nco + mixer loss 6db gain to compensate for nco + mixer loss downsample by 2 +6db +6db +6db +6db 11752-042 figure 147 . ddc theory of operation example (real input decimate by 16)
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 51 of 97 table 11 . ddc samples, chip decimation ratio = 1 real (i) output (complex to real enabled) complex (i/q) outputs (complex to real disabled) hb1 fir (dcm 1 = 1) hb2 fir + hb1 fir (dcm 1 = 2) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 4) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb1 fir (dcm 1 = 2) hb2 fir + hb1 fir (dcm 1 = 4) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 16) n n n n n n n n n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 2 n n n n n n n n + 3 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 4 n + 2 n n n + 2 n n n n + 5 n + 3 n + 1 n + 1 n + 3 n + 1 n + 1 n + 1 n + 6 n + 2 n n n + 2 n n n n + 7 n + 3 n + 1 n + 1 n + 3 n + 1 n + 1 n + 1 n + 8 n + 4 n + 2 n n + 4 n + 2 n n n + 9 n + 5 n + 3 n + 1 n + 5 n + 3 n + 1 n + 1 n + 10 n + 4 n + 2 n n + 4 n + 2 n n n + 11 n + 5 n + 3 n + 1 n + 5 n + 3 n + 1 n + 1 n + 12 n + 6 n + 2 n n + 6 n + 2 n n n + 13 n + 7 n + 3 n + 1 n + 7 n + 3 n + 1 n + 1 n + 14 n + 6 n + 2 n n + 6 n + 2 n n n + 15 n + 7 n + 3 n + 1 n + 7 n + 3 n + 1 n + 1 n + 16 n + 8 n + 4 n + 2 n + 8 n + 4 n + 2 n n + 17 n + 9 n + 5 n + 3 n + 9 n + 5 n + 3 n + 1 n + 18 n + 8 n + 4 n + 2 n + 8 n + 4 n + 2 n n + 19 n + 9 n + 5 n + 3 n + 9 n + 5 n + 3 n + 1 n + 20 n + 10 n + 4 n + 2 n + 10 n + 4 n + 2 n n + 21 n + 11 n + 5 n + 3 n + 11 n + 5 n + 3 n + 1 n + 22 n + 10 n + 4 n + 2 n + 10 n + 4 n + 2 n n + 23 n + 11 n + 5 n + 3 n + 11 n + 5 n + 3 n + 1 n + 24 n + 12 n + 6 n + 2 n + 12 n + 6 n + 2 n n + 25 n + 13 n + 7 n + 3 n + 13 n + 7 n + 3 n + 1 n + 26 n + 12 n + 6 n + 2 n + 12 n + 6 n + 2 n n + 27 n + 13 n + 7 n + 3 n + 13 n + 7 n + 3 n + 1 n + 28 n + 14 n + 6 n + 2 n + 14 n + 6 n + 2 n n + 29 n + 15 n + 7 n + 3 n + 15 n + 7 n + 3 n + 1 n + 30 n + 14 n + 6 n + 2 n + 14 n + 6 n + 2 n n + 31 n + 15 n + 7 n + 3 n + 15 n + 7 n + 3 n + 1 1 dcm means decimation.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 52 of 97 table 12 . ddc samples, chip decimation ratio = 2 real (i) output (complex to real enabled) complex (i/q) outputs (complex to real disabled) hb2 fir + hb1 fir (dcm 1 = 2) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 4) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb1 fir (dcm 1 = 2) hb2 fir + hb1 fir (dcm 1 = 4) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 16) n n n n n n n n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 2 n n n + 2 n n n n + 3 n + 1 n + 1 n + 3 n + 1 n + 1 n + 1 n + 4 n + 2 n n + 4 n + 2 n n n + 5 n + 3 n + 1 n + 5 n + 3 n + 1 n + 1 n + 6 n + 2 n n + 6 n + 2 n n n + 7 n + 3 n + 1 n + 7 n + 3 n + 1 n + 1 n + 8 n + 4 n + 2 n + 8 n + 4 n + 2 n n + 9 n + 5 n + 3 n + 9 n + 5 n + 3 n + 1 n + 10 n + 4 n + 2 n + 10 n + 4 n + 2 n n + 11 n + 5 n + 3 n + 11 n + 5 n + 3 n + 1 n + 12 n + 6 n + 2 n + 12 n + 6 n + 2 n n + 13 n + 7 n + 3 n + 13 n + 7 n + 3 n + 1 n + 14 n + 6 n + 2 n + 14 n + 6 n + 2 n n + 15 n + 7 n + 3 n + 15 n + 7 n + 3 n + 1 1 dcm means decimation. table 13 . ddc samples, chip decimation ratio = 4 real (i) output (complex to real enabled) complex (i/q) outputs (complex to real disabled) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 4) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb2 fir + hb1 fir (dcm 1 = 4) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 16) n n n n n n + 1 n + 1 n + 1 n + 1 n + 1 n + 2 n n + 2 n n n + 3 n + 1 n + 3 n + 1 n + 1 n + 4 n + 2 n + 4 n + 2 n n + 5 n + 3 n + 5 n + 3 n + 1 n + 6 n + 2 n + 6 n + 2 n n + 7 n + 3 n + 7 n + 3 n + 1 1 dcm means decimation. table 14 . ddc samples, chip decimation ratio = 8 real (i) output (complex to real enabled) complex (i/q) outputs (complex to real disabled) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb3 fir + hb2 fir + hb1 fir (dcm 1 = 8) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 16) n n n n + 1 n + 1 n + 1 n + 2 n + 2 n n + 3 n + 3 n + 1 n + 4 n + 4 n + 2 n + 5 n + 5 n + 3 n + 6 n + 6 n + 2 n + 7 n + 7 n + 3 1 dcm means decimation.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 53 of 97 table 15 . ddc samples, chip decimation ratio = 16 real (i) output (complex to real enabled) complex (i/q) outputs (complex to real disabled) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 16) hb4 fir + hb3 fir + hb2 fir + hb1 fir (dcm 1 = 16) not applicable n not applicable n + 1 not applicable n + 2 not applicable n + 3 1 dcm means decimation. if the chip decimation ratio is set to decimate by 4, ddc 0 is set to use hb2 + hb1 filters (complex outputs decimate by 4), and ddc 1 is set to use hb4 + hb3 + hb2 + hb1 filters (real outputs decimate by 8), then ddc 1 repeats its output data two times fo r every one ddc 0 output. the resulting output samples are shown in table 16. table 16 . ddc output samples when chip dcm 1 = 4, ddc 0 dcm 1 = 4 (complex), and ddc 1 dcm 1 = 8 (real) ddc 0 ddc 1 ddc input samples output port i output port q output port i output port q n i0 [n] q0 [n] i1 [n] not applicable n + 1 n + 2 n + 3 n + 4 i0 [n + 1] q0 [n + 1] i1 [n + 1] not applicable n + 5 n + 6 n + 7 n + 8 i0 [n + 2] q0 [n + 2] i1 [n] not applicable n + 9 n + 10 n + 11 n + 12 i0 [n + 3] q0 [n + 3] i1 [n + 1] not applicable n + 13 n + 14 n + 15 1 dcm means decimat ion.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 54 of 97 frequency translatio n frequency translatio n general description frequency translation is accomplished by using a 12 - bit complex nco along with a digital quadrature mixer. the frequency translation translates either a real or complex input signal from an intermediate frequency ( if) to a baseband complex digital output (carrier frequency = 0 hz). the frequency translation stage of each ddc can be controlled individually and supports four different if modes using bits[5:4] of the ddc control registers (register 0x310, register 0x33 0, register 0x350, and register 0x370). these if modes are ? variable if mode ? 0 hz if (zif) mode ? f s /4 hz if mode ? te st m o de variable if mode nco and mixers are enabled. nco output frequency can be used to digitally tune the if frequency. 0 hz if (zif) mode mixers are bypassed and the nco is disabled. f s /4 hz if mode mixers and nco are enabled in special down mixing by f s /4 mode to save power. test mode input samples are forced to 0.999 to positive full scale. nco is enabled. this test mode allows the ncos to directly drive the decimation filters. figure 148 and figure 149 show exampl es of the frequency translation stage for both real and complex inputs. bandwidth of interest bandwidth of interest image nco frequency tuning word (ftw) selection 12-bit nco ftw = mixing frequency/adc sample rate 4096 adc + digital mixer + nco real input?sampled at f s dc ? f s /2 ? f s /3 ? f s /4 ? f s /8 f s /16 f s /8 f s /4 f s /3 f s /2 ? f s /16 ? f s /32 f s /32 dc ? f s /32 f s /32 dc ? f s /32 f s /32 frv&w 0 90 i q adc sampling at f s real real vlq&w 12-bit nco positive ftw values negative ftw values complex ?6db loss due to nco + mixer 12-bit nco ftw = round (( f s /3)/ f s 4096) = +1365 (0x555) 12-bit nco ftw = round (( f s /3)/ f s 4096) = ?1365 (0xaab) 1 1752-043 figure 148 . ddc nco frequency tuning word selection real inputs
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 55 of 97 nco frequency tuning word (ftw) selection 12-bit nco ftw = mixing frequency/adc sample rate 4096 quadrature analog mixer + 2 adcs + quadrature digital mixer + nco complex input?sampled at f s ? f s /2 ? f s /3 ? f s /4 ? f s /8 f s /16 f s /8 f s /4 f s /3 f s /2 ? f s /16 ? f s /32 f s /32 ? f s /32 f s /32 dc dc 12-bit nco ftw = round (( f s /3)/ f s 4096) = +1365 (0x555) bandwidth of interest positive ftw values image due to analog i/q mismatch real i q quadrature mixer i q i ? + q q i q + + q i i complex i q Csin(t) adc sampling at f s adc sampling at f s 90 phase 12-bit nco 90 0 1 1752-044 figure 149 . ddc nco frequency tuning word selection complex inputs ddc nco plus mixer l oss and sfdr when mixing a real input signal down to baseband , 6 db of loss is introduced in the signal due to filtering of the negative image. an additional 0.05 db of loss is introduced by the nco. the total loss of a real input signal mixed down to baseband is 6.05 db . for this reason, it is recommended that the user compensate for this loss by enabling the additional 6 db of gain in the gain stage of the ddc to recenter the dynamic range of the signal within the full scale of the output bits. when mixing a complex input signal down to baseband, the maximum value each i/q sample can reach is 1.414 full scale after it passes through the complex mixer. to avoid overrange of the i/q samples and to keep the data bitwidths aligned with real mixing, 3.06 db of loss (0.707 full scale) is introduced in the mixer for co mplex signals. an additional 0.05 db of loss is introduced by the nco. the total loss of a complex input signal mixed down to baseband is ?3.11 db. the worst case spurious signal from the nco is greater than 102 dbc sfdr for all output frequencies. numerically controll ed oscillator the ad9680 has a 12 - bit nco for each ddc that enables the frequency translation process. the nco allows the input spectrum to be tuned to dc, where it can be effe ctively filtered by the subsequent filter blocks to prevent aliasing. the nco can be set up by providing a frequency tuning word (ftw) and a phase offset word (pow). setting up the nco ftw and pow the nco frequency value is given by the 12 - bit twos complem ent number entered in the nco ftw. frequencies between ?f s /2 and f s /2 (f s /2 excluded) are represented using the following frequency words: x 0x800 represents a frequency of C f s /2. x 0x000 represents dc (frequency is 0 hz). x 0x7ff represents a frequency of +f s /2 C f s /2 12 . the nco frequency tuning word can be calculated using the following equation: s s c f f f mod round ftw nco ) , ( 2 _ 12 where: nco_ftw is a 12 - bit twos complement number representing t h e n c o f t w. f s is the ad9680 sampling frequency (clock rate) in hz. f c is the desired carrier frequency in hz. mod( ) is a remainder function. for example, mod (110,100) = 10, and for negative numbers, mod ( C 32, 10) = C 2. round( ) is a rounding function. for example, round (3.6) = 4, and for negative numbers, round ( C 3.4)= C 3. note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals).
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 56 of 97 for exa mple, if the adc sampling frequency (f s ) is 1250 msps and the carrier frequency (f c ) is 416.667 mhz, mhz 1365 1250 1250 , 667 . 416 ( 2 _ 12 = ? ? ? ? ? ? = mod round ftw nco this in turn converts to in the - it twos complement representation for nco_ftw the actual carrier freuenc can e calcu lated ased on the following euation mh _ = = ? s c f ftw nco actual f a - it pow is availale for each nco to create a known phase relationship etween multiple ad chips or individual ddc channels i nside one ad the following procedure must e followed to update the ftw andor pow registers to ensure proper operation of the nco ? write to the ftw registers for all the ddcs. ? write to the p ow registers for all the ddcs. ? synchronize the ncos either through the ddc soft reset bit accessible through the spi, or through the assertion of the sysref pin. note that the ncos must be synchronized either through spi or through the sysref pin after a ll writes to the ftw or pow registers have completed. this synchronization is necessary to ensure the proper operation of the nco. nco synchronization each nco contains a separate phase accumulator word (paw) that determines the instantaneous phase of the nco. the initial reset value of each paw is determined by the pow described in the setting up the nco ftw and pow section. the phase increment value of each paw is determined by the ftw. two methods can be used to synchronize multiple paws within the chip: ? using the spi. the ddc nco soft reset bit in the ddc synchronization control register (register 0x300, bit 4) can be used to reset all the paws in the chip. this is accomplished by toggling the ddc nco soft reset bit. this method can only be used to synchronize ddc channels within the same ad9680 chip. ? using the sysref pin. when the sysref pin is enabled in the sysref control registers (register 0x120 and register 0x121), and the ddc synchronization is enabled in bits[1:0] in the ddc synchronization control register (register 0x300), any subsequent sy sref event resets all the paws in the chip. this method can be used to synchronize ddc channels within the same ad9680 chip, or ddc channels within separate ad9680 chips. mixer the nco is accompanied by a mixer, whose operation is similar to an analog quadrature mixer. the mixer performs the downconversion of input signals (real or complex) by using the nco frequency as a local oscillator . for real input signals, this mixer performs a real mixer operation (with two multipliers). for complex input signals, the mixer performs a complex mixer operation (with four multipliers and two adders). the mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. the selection of real or complex inputs can be controlled individually for each ddc block by using bit 7 of the ddc control register (register 0x310 , register 0x330, register 0x350, and register 0x370).
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 57 of 97 fir filters fir filters general description there are four sets of decimate - by - 2, low - pass, half - band, finite impulse response (fir) filters (hb1 fir, hb2 fir, hb3 fir, and hb4 fir, shown in figure 146 ). these filters follow the frequency translation stage. after the carrier of interest is tuned down to dc (carrier frequency = 0 hz), these filters efficiently lower the sample rate while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. hb1 fir is always enabled and cannot be bypassed. the hb2, hb3, and hb4 fir filters are optional and can be bypassed for higher ou tput sample rates. table 17 shows the different bandwidth options by including different half - band filters. in all cases, the ddc filtering stage of the ad9680 provides less than ?0.001 db o f pass - band ripple and >100 db of stop - band alias rejection. table 18 shows the amo unt of stop - band alias rejection for multiple pass - band ripple/cutoff points. the decimation ratio of the filtering stage of each ddc can be controlled individually through bits[1:0] of the ddc control registers (0x310, 0x330, 0x350, and 0x370). table 17 . ddc filter characteristics adc sample rate (msps) half band filter selection real output complex (i/q) output alias protected bandwidth (mhz) ideal snr improvement (db) 1 pass - band ripple (db) alias rejection (db) decimation ratio output sample rate (msps) decimation ratio output sample rate (msps) 1250 hb1 1 1250 2 625 (i) + 625 (q) 481.25 1 100 hb1 + hb2 2 625 4 312.5 (i) + 312.5 (q) 240.62 4 hb1 + hb2 + hb3 4 312.5 8 156.25 (i) + 156.25 (q) 120.31 7 hb1 + hb2 + hb3 + hb4 8 156.25 16 78.125 (i) + 78.125 (q) 60.15 10 1000 hb1 1 1000 2 500 (i) + 500 (q) 385.0 1 hb1 + hb2 2 500 4 250 (i) + 250 (q) 192.5 4 hb1 + hb2 + hb3 4 250 8 125 (i) + 125 (q) 96.3 7 hb1 + hb2 + hb3 + hb4 8 125 16 62.5 (i) + 62.5 (q) 48.1 10 820 hb1 1 820 2 410 (i) + 410 (q) 315.7 1 hb1 + hb2 2 410 4 205 (i) + 205 (q) 157.8 4 hb1 + hb2 + hb3 4 205 8 102.5 (i) + 102.5 (q) 78.9 7 hb1 + hb2 + hb3 + hb4 8 102.5 16 51.25 (i) + 51.25 (q) 39.4 10 500 hb1 1 500 2 250 (i) + 250 (q) 192.5 1 hb1 + hb2 2 250 4 125 (i) + 125 (q) 96.3 4 hb1 + hb2 + hb3 4 125 8 62.5 (i) + 62.5 (q) 48.1 7 hb1 + hb2 + hb3 + hb4 8 62.5 16 31.25 (i) + 31.25 (q) 24.1 10 1 ideal snr improvement due to oversampling and filtering = 10log(bandwidth/(f s /2)).
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 58 of 97 table 18 . ddc filter alias rejection alias rejection (db) pass - band ripple/ cutoff point (db) alias protected bandwidth for real (i) outputs 1 alias protected bandwidth for complex (i/q) outputs 1 >100 p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 59 of 97 hb2 filter the third decimate - by - 2, half - band, low - pass fir filter (hb2) uses a 19 - tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. the hb2 filter is only used when complex outputs (decimate by 4, 8, or 16) or rea l outputs (decimate by 2, 4, or 8) are enabled; otherwise, the filter is bypassed. table 21 and figure 152 show the coefficients and response of the hb2 filter. table 21 . hb2 filter coefficients hb2 coefficient number normalized coefficient decimal coefficient (19 - bit) c1, c19 0.000614 161 c2, c18 0 0 c3, c17 ?0.005066 ?1328 c4, c16 0 0 c5, c15 0.022179 5814 c6, c14 0 0 c7, c13 ?0.073517 ?19,272 c8, c12 0 0 c9, c11 0.305786 80,160 c10 0.500000 131,072 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 magnitude (db) normalized frequency ( rad/sample) 11752-047 figure 152 . hb2 filter response hb1 filter the fourth and final decimate - by - 2, half - band, low - pass fir filter (hb1) uses a 55 - tap, symmetrical, fixed coefficient filter implementation, optimized for low power consumption. the hb1 filter is always enabled and cannot be bypassed. table 22 and figure 153 show the coefficients and response of the hb1 filter. 0 ?120 ?100 ?80 ?60 ?40 ?20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 magnitude (db) normalized frequency ( rad/sample) 11752-048 figure 153 . hb1 filter response table 22 . hb1 filter coefficients hb1 coefficient number normalized coefficient decimal coefficient (21 - bit) c1, c55 ?0.000023 ?24 c2, c54 0 0 c3, c53 0.000097 102 c4, c52 0 0 c5, c51 ?0.000288 ?302 c6, c50 0 0 c7, c49 0.000696 730 c8, c48 0 0 c9, c47 ?0.0014725 ?1544 c10, c46 0 0 c11, c45 0.002827 2964 c12, c44 0 0 c13, c43 ?0.005039 ?5284 c14, c42 0 0 c15, c41 0.008491 8903 c16, c40 0 0 c17, c39 ?0.013717 ?14,383 c18, c38 0 0 c19, c37 0.021591 22,640 c20, c36 0 0 c21, c35 ?0.033833 ?35,476 c22, c34 0 0 c23, c33 0.054806 57,468 c24, c32 0 0 c25, c31 ?0.100557 ?105,442 c26, c30 0 0 c27, c29 0.316421 331,792 c28 0.500000 524,288
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 60 of 97 ddc gain stage each ddc contains an independently controlled gain stage. the gain is selectable as either 0 db or 6 db. when mixing a real input signal down to baseband, it is recommended that the user enable the 6 db of gain to recenter the dynamic range of the signal within the full scale of the output bits. when mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits and no additional gain is necessary. howe ver, the optional 6 db gain can be used to compensate for low signal strengths. the downsample by 2 portion of the hb1 fir filter is bypassed when using the complex to real conversion stage (see figure 154). ddc complex to real conversion each ddc contains an independently controlled complex to real conversion block. the complex to real conversion block reuses the last filter (hb1 fir) in the filtering stage, along with an f s /4 complex mixer to upconvert the signal. after up converting the signal, the q portion of the complex mixer is no longer needed and is dropped. figure 154 shows a simplified block diagram of the complex to real conversion. low-pass filter 2 i q real hb1 fir low-pass filter 2 hb1 fir 0 1 complex to real enable q 90 0 + ? complex to real conversion i q i q gain stage cos(t) sin(t) f s /4 i/real 0db or 6db 0db or 6db 0db or 6db 0db or 6db 1 1752-049 figure 154 . complex to real conversion block
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 61 of 97 ddc example configur ations table 23 describes the register settings for multiple ddc example configurations. table 23 . ddc example configurations chip application layer chip decimation ratio ddc input ty pe ddc output type bandwidth per ddc 1 no. of virtual converters required register settings 2 one ddc 2 complex complex 38.5% f s 2 register 0x200 = 0x01 (one ddc; i/q selected) register 0x201 = 0x01 (chip decimate by 2) register 0x310 = 0x83 (complex mixer; 0 db gain; variable if; complex outputs; hb1 filter) register 0x311 = 0x04 (ddc i input = adc channel a; ddc q input = adc channel b) register 0x314, register 0x315, register 0x320 , register 0x321 = ftw and pow set as required by application for ddc 0 two ddcs 4 complex complex 19.25% f s 4 register 0x200 = 0x02 (two ddcs; i/q selected) register 0x201 = 0x02 (chip decimate by 4) register 0x310, register 0x330 = 0x80 (complex mixer; 0 db gain; variable if; complex outputs; hb2 + hb1 filters) register 0x311, register 0x331 = 0x04 (ddc i input = adc channel a; ddc q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 two ddcs 4 complex real 9.63% f s 2 register 0x200 = 0x22 (two ddcs; i only selected) register 0x201 = 0x02 ( chip decimate by 4) register 0x310, register 0x330 = 0x89 (complex mixer; 0 db gain; variable if; real output; hb3 + hb2 + hb1 filters) register 0x311, register 0x331 = 0x04 (ddc i input = adc channel a; ddc q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 two ddcs 4 real real 9.63% f s 2 register 0x200 = 0x22 (two ddcs; i only selected) register 0x201 = 0x02 (chip decimate by 4) register 0x310, register 0x330 = 0x49 (real mixer; 6 db gain; variable if; real output; hb3 + hb2 + hb1 filters) register 0x311 = 0x00 (ddc 0 i input = adc channel a; ddc 0 q input = adc channel a) register 0x331 = 0x05 (ddc 1 i input = adc channel b; ddc 1 q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 two ddcs 4 real complex 19.25% f s 4 register 0x200 = 0x02 (two ddcs; i/q selected) register 0x201 = 0x02 (chip decimate by 4) register 0x310, register 0x330 = 0x40 (real mixer; 6 db gain; variable if; complex output; hb2 + hb1 filters) register 0x311 = 0x00 (ddc 0 i input = adc channel a; ddc 0 q input = adc channel a) register 0x331 = 0x05 (ddc 1 i input = adc channel b; ddc 1 q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 62 of 97 chip application layer chip decimation ratio ddc input ty pe ddc output type bandwidth per ddc 1 no. of virtual converters required register settings 2 two ddcs 8 real real 4.81% f s 2 register 0x200 = 0x22 (two ddcs; i only selected) register 0x201 = 0x03 (chip decimate by 8) register 0x310, register 0x330 = 0x4a (real mixer; 6 db gain; variable if; real output; hb4 + hb3 + hb2 + hb1 filters) register 0x311 = 0x00 (ddc 0 i input = adc channel a; ddc 0 q input = adc channel a) register 0x331 = 0x05 (ddc 1 i input = adc channel b; ddc 1 q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 four ddcs 8 real complex 9.63% f s 8 register 0x200 = 0x03 (four ddcs; i/q selected) register 0x201 = 0x03 (chip decimate by 8) register 0x310, register 0x330, register 0x350, register 0x370 = 0x41 (real mixer; 6 db gain; variable if; complex output; hb3+hb2+hb1 filters) register 0x311 = 0x00 (ddc 0 i input = adc channel a; ddc 0 q input = adc channel a) register 0x331 = 0x00 (ddc 1 i input = adc channel a; ddc 1 q input = adc channel a) register 0x351 = 0x05 (ddc 2 i input = adc channel b; ddc 2 q input = adc channel b) register 0x371 = 0x05 (ddc 3 i input = adc channel b; ddc 3 q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 register 0x354, register 0x355, register 0x360, register 0x361 = ftw and pow set as required by application for ddc 2 register 0x374, register 0x375, register 0x380, register 0x381 = ftw and pow set as required by application for ddc 3 four ddcs 8 real real 4.81% f s 4 register 0x200 = 0x23 (four ddcs; i only selected) register 0x201 = 0x03 (chip decimate by 8) register 0x310, register 0x330, register 0x350, register 0x370 = 0x4a (real mixer; 6 db gain; variable if; real output; hb4 + hb3 + hb2 + hb1 filters) register 0x311 = 0x00 (ddc 0 i input = adc channel a; ddc 0 q input = adc channel a) register 0x331 = 0x00 (ddc 1 i input = adc channel a; ddc 1 q input = adc channel a) register 0x351 = 0x05 (ddc 2 i input = adc channel b; ddc 2 q input = adc channel b) register 0x371 = 0x05 (ddc 3 i input = adc channel b; ddc 3 q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 register 0x354, register 0x355, register 0x360, register 0x361 = ftw and pow set as required by application for ddc 2 register 0x374, register 0x375, register 0x380, register 0x381 = ftw and pow set as required by application for ddc 3
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 63 of 97 chip application layer chip decimation ratio ddc input ty pe ddc output type bandwidth per ddc 1 no. of virtual converters required register settings 2 four ddcs 16 real complex 4.81% f s 8 register 0x200 = 0x03 (four ddcs; i/q selected) register 0x201 = 0x04 (chip decimate by 16) register 0x310, register 0x330, register 0x350, register 0x370 = 0x42 (real mixer; 6 db gain; variable if; complex output; hb4 + hb3 + hb2 + hb1 filters) register 0x311 = 0x00 (ddc 0 i input = adc channel a; ddc 0 q input = adc channel a) register 0x331 = 0x00 (ddc 1 i input = adc channel a; ddc 1 q input = adc channel a) register 0x351 = 0x05 (ddc 2 i input = adc channel b; ddc 2 q input = adc channel b) register 0x371 = 0x05 (ddc 3 i input = adc channel b; ddc 3 q input = adc channel b) register 0x314, register 0x315, register 0x320, register 0x321 = ftw and pow set as required by application for ddc 0 register 0x334, register 0x335, register 0x340, register 0x341 = ftw and pow set as required by application for ddc 1 register 0x354, register 0x355, register 0x360, register 0x361 = ftw and pow set as required by application for ddc 2 register 0x374, register 0x375, register 0x380, register 0x381 = ftw and pow set as required by application for ddc 3 1 f s is the adc sample rate. bandwidths listed are 100 db of stop - band alias rejection. 2 the ncos must be synchronized either through the spi or through the sysref pin after all writes to the ftw or pow registers have completed, to ensure the proper operation of the nco. see the nco synchronization section for more information.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 64 of 97 digital outputs introduction to the jesd204b interface the ad9680 digital outputs are designed to the jedec standard jesd204b, serial interface for data converters. jesd204b is a protocol to link the ad9680 to a digital processing device over a serial interface with lane rates of up to 12.5 gbps. the benefits of the jesd204b interface over lvds include a reduction in required board area for data interface routing, and an ability to e nable smaller packages for converter and logic devices. jesd204b overview the jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 - bit/10 - bit encoding as well as optional scrambling to form serial output data. lane s ynchronization is supported through the use of special control characters during the initial establishment of the link. additional control characters are embedded in the data stream to maintain synchronization thereafter. a jesd204b receiver is required to complete the serial link. for additional details on the jesd204b interface, refer to the jesd204b standard. the ad9680 jesd204b data transmit block maps up to two physical adcs or up to eight vir tual converters (when ddcs are enabled) over a link. a link can be configured to use one, two, or four jesd204b lanes. the jesd204b specification refers to a number of parameters to define the link, and these parameters must match between the jesd204b tran smitter (the ad9680 output) and the jesd204b receiver (the logic device input). the jesd204b link is described according to the following parameters: ? l is the number of lanes/converter device (lan es/link) ( ad9680 value = 1, 2, or 4) ? m is the number of converters/converter device (virtual converters/link) ( ad9680 value = 1, 2, 4, or 8) ? f is the octets/frame ( ad9680 value = 1, 2, 4, 8, or 16) ? n? is the number of bits per sample (jesd204b word size) ( ad9680 value = 8 or 16) ? n is the converter resolution ( ad9680 value = 7 to 16) ? cs is the number of control bits/sample ( ad9680 value = 0, 1, 2, or 3) ? k is the number of frames per multiframe ( ad9680 value = 4, 8, 12, 16, 20, 24, 28, or 32 ) ? s is the samples transmitted/single converter/frame cycle ( ad9680 value = set automatically based on l, m, f, and n?) ? hd is the high density mode ( ad9680 = set automatically based on l, m, f, and n?) ? cf is the number of control words/frame clock cycle/ converter device ( ad9680 value = 0) figure 155 shows a simplified bloc k diagram of the ad9680 jesd204b link. by default, the ad9680 is configured to use two converters and four lanes. converter a data is output to serdout0 and/or serdout1, and converter b is output to serdout2 and/or serdout3. the ad9680 allows other conf igurations such as combining the outputs of both converters onto a single lane, or changing the mapping of the a and b digital output paths. these modes are set up via a quick configuration register in the spi register map, along with additional customizab le options. by default in the ad9680 , the 14 - bit converter word from each converter is broken into two octets (eight bits of data). bit 13 (msb) through bit 6 are in the first octet. the second oc tet contains bit 5 through bit 0 (lsb) and two tail bits. the tail bits can be configured as zeros or a pseudorandom number sequence. the tail bits can also be replaced with control bits indicating overrange, sysref, or fast detect output. the two resulti ng octets can be scrambled. scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. the scrambler uses a self - synchronizing, polynomial - based algorithm defined by the equation 1 + x 14 + x 1 5 . the descrambler in the receiver is a self - synchronizing version of the scrambler polynomial. the two octets are then encoded with an 8 - bit/10 - bit encoder. the 8 - bit/10 - bit encoder works by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. figure 156 shows how the 14 - bit data is taken from the adc, how the tail bits are added, how the two octets are scrambled, and how the octets are encoded into two 10 - bit symbols. figure 156 illustrates the default data format. adc a adc b sysref syncinb converter a input converter b input converter 0 converter 1 serdout0?, serdout0+ serdout1?, serdout1+ serdout2?, serdout2+ serdout3?, serdout3+ lane mux and mapping (spi reg 0x5b0, reg 0x5b2, reg 0x5b3, reg 0x5b5, reg 0x5b6) jesd204b link control (l.m.f) (spi reg 0x570) mux/ format (spi reg 0x561, reg 0x564) 1 1752-050 figure 155 . transmit link simplified block diagram showing full bandwidth mode (register 0x200 = 0x00)
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 65 of 97 8 - b i t / 10 - b i t e nc o d e r se rd o u t 0 se rd o u t 1 t a i l b i t s 0x571[6] se r i a l i z e r ad c sy m b o l 0 sy m b o l 1 a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 c2 c1 c0 m s b l s b control bits adc t es t p a tt e rn s ( r e 0x550 , r e g 0x551 t o r e g 0x558 ) j es d 204 b s a m p l e c o n s t ruc t io n j es d 204 b interface t es t p a tt e rn ( r e g 0x57 3, r e g 0x551 t o r e g 0x558 ) f ra m e c o n s t ruc t io n jesd204b data link layer test patterns r e g 0x574 [2:0] s cra m b l e r 1 + x 1 4 + x 1 5 ( o p t io na l ) a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 c 2 t m s b l s b o c t e t 0 o c t e t 1 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 m s b l s b o c t e t 0 o c t e t 1 a b c d e f g h i j a b c d e f g h i j a b i j a b i j 1 1752 - 05 1 j es d 204 b long transport t es t p a tt e rn r e g 0x571 [5] figure 156 . adc output data path showing data framing transport layer physical layer data link layer tx output sample construction frame construction scrambler alignment character generation 8-bit/10-bit encoder crossbar mux serializer processed samples from adc sysref syncinb 1 1752-052 figure 157 . data flow func tional overview the block diagram in figure 157 shows the flow of data through the jesd204b hardware from the sample input to the physical output. the processing can b e divided into layers that are derived from the open source initiative (osi) model widely used to describe the abstraction layers of communications systems. these layers are the transport layer, data link layer, and physical layer (serializer and output dr iver). transport layer the transport layer handles packing the data (consisting of samples and optional control bits) into jesd204b frames that are mapped to 8 - bit octets. these octets are sent to the data link layer. the transport layer mapping is control led by rules derived from the link parameters. tail bits are added to fill gaps where required. the following equation can be used to determine the number of tail bits within a sample (jesd204b word): t = n? C n C cs data link layer the data link layer is responsible for the low level functions of passing data across the link. these include optionally scrambling the data, inserting control characters for multichip synchronization/lane alignment/monitoring, and encoding 8 - bit octets into 10 - bit symbols. the data link layer is also responsible for sending the initial lane alignment sequence (ilas), which contains the link configuration data used by the receiver to verify the settings in the transport layer. physical layer the physical layer consists of the hig h speed circuitry clocked at the serial clock rate. in this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. jesd204b link establ ishment the a d9680 jesd204b transmitter (tx) interface operates in subclass 1 as defined in the jedec standard 204b (july 2011 specification). the link establishment process is divided into the following steps: code group synchronization and syncinb, initial lane alig nment sequence, and user data and error correction. code group synchronization (cgs) and syncinb the cgs is the process by which the jesd204b receiver finds the boundaries between the 10 - bit symbols in the stream of data. during the cgs phase, the jesd204 b transmit block transmits /k28.5/ characters. the receiver must locate /k28.5/ characters in its input data stream using clock and data recovery (cdr) techniques. the receiver issues a synchronization request by asserting the syncinb pin of the ad9680 low. the jesd204b tx then begins sending /k/ characters. once the receiver has synchronized, it waits for the correct reception of at least four consecutive /k/ symbols . it then deasserts syncinb. the ad9680 then transmits an ilas on the following local multiframe clock (lmfc) boundary. for more information on the code group synchronization phase, refer to the jedec standard jesd204b, july 2011, section 5.3.3.1.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 66 of 97 the syncinb pin operation can also be controlled by the spi. the syncinb signal is a differential dc - coupled lvds mode signal by default, but it can also be driven single - ended. for more information on configuring the syncinb pin operation, refer to register 0x572. the syncinb pins can also be configured to run in cmos (single - ended) mode, by setting bit[4] in register 0x572. when running syncinb in cmos mode, connect the cmos syncinb signal to pin 21 (syncinb+) and leave pin 20 (syncinb?) floating. initial lane alignment sequence (ilas) the ilas phase follows the cgs phase and begins on the next lmfc boundary . the ilas consists of four mul t i frames, with an /r/ character marking the beginning and an /a/ character marking the end. the ilas begins by sending an /r/ character followed by 0 to 255 ramp data for one multiframe. on the second multiframe, the link configuration data is sent, starting with the third character. the second character is a /q/ character to confirm that the lin k configuration data will follow. all undefined data slots are filled with ramp data. the ilas sequence is never scrambled. the ilas sequence construction is shown in figure 158 . the four multiframes include the following: ? multiframe 1. begins with an /r/ character (/k28.0/) and ends with an /a/ character (/k28.3/). ? multiframe 2. begins with an /r/ character followed by a /q/ character (/k28.4/), followed by link config uration parameters over 14 configuration octets (see table 24 ) and ends with an /a/ character. many of the parameter values are of the value C 1 notati on. ? multiframe 3. begins with an /r/ character (/k28.0/) and ends with an /a/ character (/k28.3/). ? multiframe 4. begins with an /r/ character (/k28.0/) and ends with an /a/ character (/k28.3/). user data and error detection after the initial lane alignment sequence is complete, the user data is sent. normally, within a frame, all characters are considered user data. however, to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /f/ or /a/ alignme nt characters when the data meets certain conditions. these conditions are different for unscrambled and scrambled data. the scrambling operation is enabled by default, but it can be disabled using the spi. for scrambled data, any 0xfc character at the end of a frame is replaced by an /f/, and any 0x7c character at the end of a multiframe is replaced with an /a/. the jesd204b receiver (rx) checks for /f/ and /a/ characters in the received data stream and verifies that they only occur in the expected locatio ns. if an unexpected /f/ or /a/ character is found, the receiver handles the situation by using dynamic realignment or asserting the syncinb signal for more than four frames to initiate a resynchronization. for unscrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /f/ if it is at the end of a frame, and an /a/ if it is at the end of a multiframe. insertion of alignment characters can be modified using spi. the frame alignment character insertio n (faci) is enabled by default. more information on the link controls is available in the memory map section, register 0x571. 8 - bit/10 - bit encoder the 8 - bit/10 - bit en coder converts 8 - bit octets into 10 - bit symbols and inserts control characters into the stream when needed. the control characters used in jesd204b are shown in table 24. the 8 - bit/10 - bit encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. the 8 - bit/10 - bit interface has options that can be controlled via the spi. these operations include byp ass and invert. these options are troubleshooting tools for the verification of the digital front end (dfe). see the memory map section, register 0x572 [2:1] for information on configuring the 8 - bit/10 - bit encoder. k k r d d a r q c c d d a r d d a r d d a d start of ilas start of link configuration data end of multiframe start of user data 1 1752-053 figure 158 . initial lane alignment sequence
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 67 of 97 table 24. ad9680 control characters used in jesd204b abbreviation control symbol 8 - bit value 10- bit value, rd 1 = ?1 10- bit value, rd 1 = +1 description /r/ /k28.0/ 000 11100 001111 0100 110000 1011 start of multiframe /a/ /k28.3/ 011 11100 001111 0011 110000 1100 lane alignment /q/ /k28.4/ 100 11100 001111 0100 110000 1101 start of link configuration data /k/ /k28.5/ 101 11100 001111 1010 110000 0101 group synchronization /f/ /k28.7/ 111 11100 001111 1000 110000 0111 frame alignment 1 rd means running disparity. physical layer (driv er) outputs digital outputs, timing, and controls the ad9680 physical layer consists of drivers that are defined in the jedec standard jesd204b, july 2011. the differential digital outputs are powered up by default. the drivers use a dynamic 100 internal termination to reduce unwanted reflections. place a 100 ? differential termination resistor at each receiver input to result in a nominal 300 mv p - p swing at the receiver (see figure 159 ). alternatively, single - ended 50 ? termination can be used. when single - ended termination is used, the termination voltage is drvdd/2. otherwise, 0.1 f ac coupling capacitors can be used to terminate to any single - ended voltage. or serdoutx+ drvdd v rxcm serdoutx? output swing = 300mv p-p 0.1f 100 50 50 0.1f receiver v cm = v rxcm 100 differential trace pair 1 1752-054 figure 159 . ac - coupled digital output termination example the ad9680 digital outputs can interface with custom asics and fpga rece ivers, providing superior switching performance in noisy environments. single point - to - point network topologies are recommended with a single differential 100 termination resistor placed as close to the receiver inputs as possible. the common mode of the digital output automatically biases itself to half the drvdd supply of 1.2 v (v cm = 0.6 v). see figure 160 for dc coupling the outputs to the receiver logic. serdoutx+ drvdd serdoutx? output swing = 300mv p-p 100 receiver v cm = drvdd/2 100 differential trace pair 1 1752-055 figure 160 . dc - coupled digital output termination example if there is no far - end receiver termination, or if there is poor differential trace routing, timing errors can result. to avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. figure 161 to figure 166 show an example of the digital output data eye, time interval error (tie) jitter histogram, and bathtub curve for one ad9680 lane running at 10 gbps and 6 gbps, respectively. the format of the output data is twos complement by default. to change the output data format, see the memory map section (register 0x561 in table 36). de - emphasis de - emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the jesd204b specification. use the de - emphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. under normal conditions, it is disabled to conserve power. a dditionally, enabling and setting too high a de - emphasis value on a short link can cause the receiver eye diagram to fail. use the de - emphasis setting with caution because it can increase electromagnetic interference (emi). see the me mory map section (register 0x5c1 to register 0x5c5 in table 36 ) for more details. phase - locked loo p the phase - locked loop (pll) is used to generate the serializer clock, which operates at the jesd204b lane rate. the status of the pll lock can be checked in the pll locked status bit (register 0x56f, bit 7). this read only bit lets the user know if the p ll has achie ved a lock for the specific setup. the jesd204b lane rate control, bit 4 of register 0x56e, must be set to correspond with the lane rate.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 68 of 97 400 ?400 ?300 ?200 ?100 0 100 200 300 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 voltage (mv) time (ps) tx eye mask 1 1752-500 figure 161 . digital outputs data eye, external 100 ? terminations at 10 gbps 12000 10000 8000 6000 4000 2000 0 ?4 ?2 0 2 4 6 hits time (ps) 1 1752-501 figure 162 . digital outputs histogram, external 100 terminations at 10 gbps 1 1 ?2 1 ?4 1 ?6 1 ?8 1 ?10 1 ?12 1 ?16 1 ?14 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ber ui 1 1752-502 figure 163 . digital outputs bathtub curve, external 100 terminations at 10 gbps 400 ?400 ?300 ?200 ?100 0 100 200 300 ?150 ?100 ?50 0 50 100 150 voltage (mv) time (ps) tx eye mask 1 1752-503 figure 164 . digital outputs data eye, external 100 terminations at 6 gbps 8000 6000 4000 2000 7000 4000 3000 1000 0 ?4 ?3 ?2 ?1 0 1 3 2 4 hits time (ps) 1 1752-504 figure 165 . digital outputs histogram, external 100 terminations at 6 gbps 1 1 ?2 1 ?4 1 ?6 1 ?8 1 ?10 1 ?12 1 ?16 1 ?14 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ber ui 1 1752-505 figure 166 . digital outpu ts bathtub curve, external 100 terminations at 6 gbps
pr o duct overview o nline documentation design resources discussion sample & buy data sheet ad9680 rev. c | page 69 of 97 jesd204b tx converter mapping to support the different chip operating modes, the ad9680 design treats each sample stream (real or i/q) as originating from separate virtual converters. the i/q samples are always mapped in pairs with the i samples mapped to the first virtual converter and the q samples mapped to the second virtual converter. with this transport layer mapping, the number of virtual converters are the same whether ? a single real converter is used along with a digital downconverter block producing i/q outputs, or ? an analog downconversion is used with two real converters producing i/q outputs. figure 167 shows a block diagram of the two scenarios described for i/q transport layer mapping. the jesd204b tx block for ad9680 supports up to four ddc blocks. each ddc block outputs either two sample streams (i/q) for the complex data components (real + imaginary), or one sample stream for real (i) data. the jesd204b interface can be configured to use up to eight virtual converters depending on the ddc configuration. figure 168 shows the virtual converters and their relationship to the ddc outputs when complex outputs are used. table 25 shows the virtual converter mapping for each chip operating mode when channel swapping is disabled. real i q i converter 0 q converter 1 adc adc 90 phase jesd204b tx l lanes i/q analog mixing m = 2 adc real real i converter 0 q converter 1 jesd204b tx l lanes digital downconversion m = 2 digital down conversion 11752-058 figure 167. i/q transport layer mapping ddc 0 i q i q real/i converter 0 q converter 1 real/i real/q ddc 1 i q i q real/i converter 2 q converter 3 real/i real/q ddc 2 i q i q real/i converter 4 q converter 5 real/i real/q ddc 3 i q i q real/i converter 6 q converter 7 real/i real/q output interface i/q crossbar mux adc a sampling at f s real/i adc b sampling at f s real/q 11752-059 figure 168. ddcs and virtual converter mapping
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 70 of 97 table 25. virtual converter mapping number of virtual converters supported chip operating mode (0x200, bits[1:0]) chip q ignore (0x200, bit 5) virtual converter mapping 0 1 2 3 4 5 6 7 1 to 2 full bandwidth mode (0x0) real or complex (0x0) adc a samples adc b samples unused unused unused unused unused unused 1 one ddc mode (0x1) real (i only) (0x1) ddc 0 i samples unused unused unused unused unused unused unused 2 one ddc mode (0x1) complex (i/q) (0x0) ddc 0 i samples ddc 0 q samples unused unused unused unused unused unused 2 two ddc mode (0x2) r eal (i o nly) (0x1) ddc 0 i samples ddc 1 i samples unused unused unused unused unused unused 4 two ddc mode (0x2) complex (i/q) (0x0) ddc 0 i samples ddc 0 q samples ddc 1 i samples ddc 1 q samples unused unused unused unused 4 four ddc mode (0x3) r eal (i o nly) (0x1) ddc 0 i samples ddc 1 i samples ddc 2 i samples ddc 3 i samples unused unused unused unused 8 four ddc mode (0x3) complex (i/q) (0x0) ddc 0 i samples ddc 0 q samples ddc 1 i samples ddc 1 q samples ddc 2 i samples ddc 2 q samples ddc 3 i samples ddc 3 q samples
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 71 of 97 configuring the jesd 204b link the ad9680 has one jesd204b link. the device offers an easy way to set up the jesd204b link through the jesd04b quick configuration register (register 0x570). the serial outputs (serdout0 to serdout3) are considered to be part of one jesd204b link. the basic parameters that determine the link setup are ? number of lanes per link (l) ? number of converters per link (m) ? number of octets per frame (f) if the internal ddcs are used for on - chip digital processi ng, m represents the number of virtual converters. the virtual converter mapping setup is shown in figure 168. the maximum lane rate allowed by the jesd204b specification is 12.5 gbps. the lane line rate is related to the jesd204b parameters using the following equation: l f n m rate line lane out ? ? ? ? ? ? = 8 10 ' where ratio decimation f f clock adc out _ = power down the link. 2. select quick configuration options. 3. configure detailed options. 4. set output lane m apping (optional). 5. set additional driver configuration options (optional). 6. power up the link. if the lane line rate calculated is less than 6.25 gbps, select the low line rate option by programming a value of 0x10 to register 0x56e. table 26 and table 27 show the jesd204b output configurations support ed for both n? = 16 and n? = 8 for a given number of virtual converters. take care to ensure that the serial line rate for a given configuration is within the supported range of 3.125 gbps to 12.5 gbps. table 26. jesd204b output configurations for n? = 16 number of virtual converters supported (same value as m) jesd204b quick configuration (0x570) jesd204b serial line rate 1 jesd204b transport layer settings 2 l m f s hd n n? cs k 3 1 0x01 20 f out 1 1 2 1 0 8 to 16 16 0 to 3 only valid k values that are divisible by 4 are supported 0x40 10 f out 2 1 1 1 1 8 to 16 16 0 to 3 0x41 10 f out 2 1 2 2 0 8 to 16 16 0 to 3 0x80 5 f out 4 1 1 2 1 8 to 16 16 0 to 3 0x81 5 f out 4 1 2 4 0 8 to 16 16 0 to 3 2 0x0a 40 f out 1 2 4 1 0 8 to 16 16 0 to 3 0x49 20 f out 2 2 2 1 0 8 to 16 16 0 to 3 0x88 10 f out 4 2 1 1 1 8 to 16 16 0 to 3 0x89 10 f out 4 2 2 2 0 8 to 16 16 0 to 3 4 0x13 80 f out 1 4 8 1 0 8 to 16 16 0 to 3 0x52 40 f out 2 4 4 1 0 8 to 16 16 0 to 3 0x91 20 f out 4 4 2 1 0 8 to 16 16 0 to 3 8 0x1c 160 f out 1 8 16 1 0 8 to 16 16 0 to 3 0x5b 80 f out 2 8 8 1 0 8 to 16 16 0 to 3 0x9a 40 f out 4 8 4 1 0 8 to 16 16 0 to 3 1 f out = output sample rate = adc sample rate/ chip decimation ratio . the jesd204b serial lin e rate must be 312 5 mbps and 12, 500 mbps ; when the serial line rate is 12 .5 g bps and 6 . 25 g bps, the low line rate mode must be disabled (set bit 4 to 0x0 in 0x 56e). when the serial line rate is < 6 . 25 gbps and 3 . 125 g bps, the low line rate mode must be enabled (set bit 4 to 0x 1 in 0x 56e) . 2 jesd204b transport layer descriptions are as described in the jesd204b overview section. 3 for f = 1, k = 20, 24, 28, and 32. for f = 2, k = 12, 16, 20, 24, 28, and 32. for f = 4, k = 8, 12, 16, 20, 24, 28, and 32. f or f = 8 and f = 16 , k = 4, 8, 12, 16, 20, 24, 28, and 32.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 72 of 97 table 27. jesd204b output configurations for n? = 8 number of virtual converters supported (same value as m) jesd204b quick configuration (0x570) serial line rate 1 jesd204b transport layer settings 2 l m f s hd n n? cs k 3 1 0x00 10 f out 1 1 1 1 0 7 to 8 8 0 to 1 only valid k values which are divisible by 4 are supported 0x01 10 f out 1 1 2 2 0 7 to 8 8 0 to 1 0x40 5 f out 2 1 1 2 0 7 to 8 8 0 to 1 0x41 5 f out 2 1 2 4 0 7 to 8 8 0 to 1 0x42 5 f out 2 1 4 8 0 7 to 8 8 0 to 1 0x80 2.5 f out 4 1 1 4 0 7 to 8 8 0 to 1 0x81 2.5 f out 4 1 2 8 0 7 to 8 8 0 to 1 2 0x09 20 f out 1 2 2 1 0 7 to 8 8 0 to 1 0x48 10 f out 2 2 1 1 0 7 to 8 8 0 to 1 0x49 10 f out 2 2 2 2 0 7 to 8 8 0 to 1 0x88 5 f out 4 2 1 2 0 7 to 8 8 0 to 1 0x89 5 f out 4 2 2 4 0 7 to 8 8 0 to 1 0x8a 5 f out 4 2 4 8 0 7 to 8 8 0 to 1 1 f out = output sample rate = adc sample rate/ chip decimation ratio . the jesd 204b serial line rate must be 3125 mbps a nd 12, 500 mbps ; when the serial line rate is 12 .5 gbps and 6 . 25 g bps, the low line rate mode must be disabled (set bit 4 to 0x0 in register 0x 56e). when the serial line rate is < 6 . 25 gbps and 3 . 125 g bps, the low line rate mode must be enabled (set bit 4 to 0x 1 in register 0x 56e) . 2 jesd204b transport layer descriptions are as described in the jesd204b overview section. 3 for f = 1, k = 20, 24, 28, and 32. for f = 2 , k = 12, 16, 20, 24, 28, and 32. for f = 4, k = 8, 12, 16, 20, 24, 28, and 32. f or f = 8 and f = 16 , k = 4, 8, 12, 16, 20, 24, 28, and 32. see the example 1: full bandwidth mode section and the example 2: adc with ddc option (two adcs plus four ddcs) section for two examples describing which jesd204b transport layer settings are valid for a given chip mode. example 1: full bandwidth mode chip application mode = full bandwidth mode (see figure 169). ? two 14 - bit converters at 1000 msps ? full bandwidth application layer mode ? no decimation jesd204b output configuration is as follows : ? two virtual converters required (see table 26) ? output sample rate (f out ) = 1000/1 = 1000 msps jesd204b supported output configurations (see table 26) include: ? n? = 16 bits ? n = 14 bits ? l = 4, m = 2, and f = 1, or l = 4, m = 2, and f = 2 (quick configuration = 0x88 or 0x89) ? cs = 0 to 2 ? k = 32 ? output se rial line rate = 10 gbps per lane, low line rate mode disabled jesd204b transmit interface fast detection fast detection cmos cmos converter 0 converter 1 14-bit at 1gbps real/i 14-bit at 1gbps real/q l jesd204b lanes a t u p t o 12.5gbps 1 1752-060 figure 169 . full bandwidth mode example 2 adc with ddc option (two adcs plus four ddcs) chip application mode = four - ddc mode. (see figure 170). ? two 14 - bit converters at 1 gsps ? four ddc application layer mode with complex outputs (i/q) ? chip decimation ratio = 16 ? ddc decimation ratio = 16 (see table 15). jesd204b output configuration is as follows : ? virtual converters required = 8 (see table 26) ? output sample rate (f out ) = 1000/16 = 62.5 msps
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 73 of 97 jesd204b supported output configurations (see table 26): ? n? = 16 bits ? n = 14 bits ? l = 1, m = 8, and f = 16, or l = 2, m = 8, and f = 8 (quick configuration = 0x1c or 0x5b) ? cs = 0 to 1 ? k = 32 ? output serial line rate = 10 gbps per lane (l = 1) or 5 gbps per lane (l = 2) for l = 1, low line rate mode is disabled. for l = 2, low line rate mode is enabled. example 2 shows the flexibility in the digital and lane configurations for the ad9680 . the sample rate is 1 gsps; however, the outputs are all combined in either one or two lanes, depending on the i/o speed capability of the receiving device. ddc 0 i converter 0 q converter 1 real/i ddc 1 i converter 2 q converter 3 real/q ddc 2 i converter 4 q converter 5 real/i ddc 3 i converter 6 q converter 7 real/q i/q crossbar mux adc a sampling at f s real adc b sampling at f s real synchronization control circuits sysref 1 1752-061 l jesd204b lanes up to 12.5gbps l jesd204b lanes at up to 12.5gbps figure 170 . two adc plus four ddc mode
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 74 of 97 multichip synchroniz ation the ad9680 has a sysref input that provides flexible options for synchronizing the internal blocks. the sysref input is a source synchronous system reference signal that enables multichip synchronization. the input clock divider, ddcs, signal monitor block, and je sd204b link can be synchronized using the sysref input. for the highest level of timing accuracy, sysref must meet setup and hold requirements relative to the clk input. the flowchart in figure 171 describes the internal mechanism for multichip synchronization in the ad9680 . the ad9680 supports sev eral features that aid users in meeting the requirements set out for capturing a sysref signal. the sysref sample event can be defined as either a synchronous low to high transition, or a synchronous high to low transition. additionally, the ad9680 allows the sysref signal to be sampled using either the rising edge or falling edge of the clk input. the ad9680 also has the ability to ignore a programmable number (up to 16) of sysref events. the sysref control options can be selected using register 0x120 and register 0x121.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 75 of 97 yes update setup/hold detector status (0x128) increment sysref ignore counter yes no sysref enabled? (0x120) no clock divider > 1? (0x10b) yes no input clock divider alignment required? yes no no yes align clock divider phase to sysref synchronization mode? (0x1ff) timestamp mode normal mode yes sysref inserted in jesd204b control bits back to start no ddc nco alignment enabled? (0x300) yes no no yes send k28.5 characters normal jesd204b initialization sysref control bits? (0x559, 0x55a, 0x58f) reset sysref ignore counter no start sysref asserted? yes no yes align signal monitor counters yes no no yes no increment sysref counter (0x12a) sysref timestamp delay (0x123) back to start sysref ignore counter expired? (0x121) clock divider auto adjust enabled? (0x10d) ramp test mode enabled? (0x550) sysref resets ramp test mode generator jesd204b lmfc alignment required? align phase of all internal clocks (including lmfc) to sysref send invalid 8-bit/10-bit characters (all 0's) sync~ asserted signal monitor alignment enabled? (0x26f) align ddc nco phase accumulator 1 1752- 1 12 figure 171 . multichip synchronization
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 76 of 97 sysref setup/hold w indow monitor to ensure a valid sysref signal capture, the ad9680 has a sysref setup/hold window monitor. this feature allows the system designer to determine the location of the sysref signals relative to the clk signals by reading back the amount of se tup/hold margin on the interface through the memory map. figure 172 and figure 173 show the setup and hold status values for different phases of sysref. the setup detector returns the status of the sysref signal before the clk edge, and the hold detector returns the status of the sysref signal after the clk edge. register 0x128 stores the status of sysref and lets the user know if the sysref signal is captured by the adc. valid reg 0x128[3:0] clk input sysref input flip-flop hold (min) flip-flop hold (min) flip-flop setup (min) 1 1752- 1 13 0 x f 0 x e 0 x d 0 x c 0 x b 0 x a 0 x 9 0 x 8 0 x 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 figure 172 . sysref setup detector
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 77 of 97 clk input sysref input valid reg 0x128[7:4] flip-flop hold (min) flip-flop hold (min) flip-flop setup (min) 1 1752- 1 14 0 x f 0 x e 0 x d 0 x c 0 x b 0 x a 0 x 9 0 x 8 0 x 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 0 figure 173 . sysref hold detector table 28 shows the description of the contents of register 0x128 and how to interpret them. table 28 . sysref setup/hold monitor, register 0x128 register 0x128[7:4] hold status register 0x128[3:0] setup status description 0x0 0x0 to 0x7 possible setup error. the smaller this number, the smaller the setup margin. 0x0 to 0x8 0x8 no setup or hold error (best hold margin). 0x8 0x9 to 0xf no setup or hold error (best setup and hold margin). 0x8 0x0 no setup or hold error (best setup margin). 0x9 to 0xf 0x0 possible hold error. the larger this number, the smaller the hold margin. 0x0 0x0 possible setup or hold error.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 78 of 97 test modes adc test modes the ad9680 has various test options that aid in the system level implementation. the ad9680 has adc test modes that are available in register 0x550. these test modes are described in t able 29. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back - end blocks, and the test pattern is run through the output formatting block . some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x550. these tests can be performed with or without an analog signal (if present , the analog signal is ignored); however, they do require an encode clock. if the application mode is set to select a ddc mode of operation, the test modes must be enabled for each ddc enabled. the test patterns can be enable d via bit 2 and bit 0 of regis ter 0x327, register 0x347, and register 0x367 , depending on which ddc(s) are selected. the (i) data uses the test patterns selected for channel a, and the (q) data uses the test patterns selected for channel b. for ddc3 only, the (i) data uses the test pat terns from channel a, and the (q) data does not output test patterns. bit 0 of register 0x387 selects the channel a test patterns to be used for the (i) data. for more information, see the an - 877 application note, interfacing to high speed adcs via spi . table 29 . adc test modes 1 output test mode bit sequence pattern name expression default/ seed value sample (n, n + 1, n + 2, ) 0000 off (default) n/a n/a n/a 0001 midscale short 00 0000 0000 0000 n/a n/a 0010 +full - scale short 01 1111 1111 1111 n/a n/a 0011 ?full - scale short 10 0000 0000 0000 n/a n/a 0100 checkerboard 10 1010 1010 1010 n/a 0x1555, 0x2aaa, 0x1555, 0x2aaa, 0x1555 0101 pn sequence long x 23 + x 18 + 1 0x3aff 0x3fd7, 0x0002, 0x26e0, 0x0a3d, 0x1ca6 0110 pn sequence short x 9 + x 5 + 1 0x0092 0x125b, 0x3c9a, 0x2660, 0x0c65, 0x0697 0111 one - /zero - word toggle 11 1111 1111 1111 n/a 0x0000, 0x3fff, 0x0000, 0x3fff, 0x0000 1000 user input register 0x551 to register 0x558 n/a user pattern 1[15:2], user pattern 2[15:2], user pattern 3[15:2], user pattern 4[15:2], user pattern 1[15:2] for repeat mode user pattern 1[15:2], user pattern 2[15:2], user pattern 3[15:2], user pattern 4 [15:2], 0x0000 for single mode 1111 ramp output (x) % 2 14 n/a (x) % 2 14 , (x +1) % 2 14 , (x +2) % 2 14 , (x +3) % 2 14 1 n/a means not applicable.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 79 of 97 jesd204b block test modes in addition to the adc pipeline test modes , the ad9680 also has flexible test modes in the jesd204b block. these test modes are listed in register 0x573 and register 0x574. these test patterns can be injected at various points along the output da ta path. these test injection points are shown in figure 156. table 30 descr ibes the various test modes available in the jesd204b block. for the ad9680 , a transition from test modes (register 0x573 0x00) to normal mode (register 0x573 = 0x00) requires an spi soft reset. this is done by writing 0x81 to register 0x00 (self cleared). transport layer sample test mode the transport layer samples are implemented in the ad9680 as defined by s ection 5.1.6.3 in the jedec jesd204b specification . these tests are shown in register 0x571[5]. the test pattern is equivalent to the raw samples from the adc. interface test modes the interface test modes are described in register 0x573, bits[3:0]. these test modes are also explain ed in table 30 . the interface tests can be injected at various points along the data. see figure 156 for more information on the test injection points . register 0x573, bits[5:4] show where these tests are injected. table 31, table 32 , and table 33 show examples of some of the te st modes when injected at the jesd sample input , phy 10 - bit input , and scrambler 8 - bit input . up in the tables represent the user pattern control bits from the customer register map. table 30 . jesd204b interface test modes output test mode bit sequence pattern name expression default 0000 off (default) not applicable not applicable 0001 alternating checker board 0x5555, 0xaaaa, 0x5555, not applicable 0010 1/0 word toggle 0x0000, 0xffff, 0x0000, not applicable 0011 31- bit pn sequence x 31 + x 28 + 1 0x0003afff 0100 23- bit pn sequence x 23 + x 18 + 1 0x003aff 0101 15- bit pn sequence x 15 + x 14 + 1 0x03af 0110 9 - bit pn sequence x 9 + x 5 + 1 0x092 0111 7 - bit pn sequence x 7 + x 6 + 1 0x07 1000 ramp output (x) % 2 16 ramp size depends on test injection point 1110 continuous/repeat user test register 0x551 to register 0x558 user pattern 1 to user pattern 4, then repeat 1111 single user test register 0x551 to register 0x558 user pattern 1 to user pattern 4, then zeros table 31. jesd204b sample input for m = 2, s = 2, n' = 16 (register 0x573[5:4] = 'b00) frame number converter number sample number alternating checkerboard 1/0 word toggle ramp pn9 pn23 user repeat user single 0 0 0 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 0 0 1 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 0 1 0 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 0 1 1 0x5555 0x0000 (x) % 2 16 0x496f 0xff5c up1[15:0] up1[15:0] 1 0 0 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 1 0 1 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 1 1 0 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 1 1 1 0xaaaa 0xffff (x +1) % 2 16 0xc9a9 0x0029 up2[15:0] up2[15:0] 2 0 0 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 2 0 1 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 2 1 0 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 2 1 1 0x5555 0x0000 (x +2) % 2 16 0x980c 0xb80a up3[15:0] up3[15:0] 3 0 0 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 3 0 1 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 3 1 0 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 3 1 1 0xaaaa 0xffff (x +3) % 2 16 0x651a 0x3d72 up4[15:0] up4[15:0] 4 0 0 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 4 0 1 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 4 1 0 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000 4 1 1 0x5555 0x0000 (x +4) % 2 16 0x5fd1 0x9b26 up1[15:0] 0x0000
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 80 of 97 table 32 . physical layer 10 - bit input (register 0x573[5:4] = 'b01) 10- bit symbol number alternating checkerboard 1/0 word toggle ramp pn9 pn23 user repeat user single 0 0x155 0x000 (x) % 2 10 0x125 0x3fd up1[15:6] up1[15:6] 1 0x2aa 0x3ff (x + 1) % 2 10 0x2fc 0x1c0 up2[15:6] up2[15:6] 2 0x155 0x000 (x + 2) % 2 10 0x26a 0x00a up3[15:6] up3[15:6] 3 0x2aa 0x3ff (x + 3) % 2 10 0x198 0x1b8 up4[15:6] up4[15:6] 4 0x155 0x000 (x + 4) % 2 10 0x031 0x028 up1[15:6] 0x000 5 0x2aa 0x3ff (x + 5) % 2 10 0x251 0x3d7 up2[15:6] 0x000 6 0x155 0x000 (x + 6) % 2 10 0x297 0x0a6 up3[15:6] 0x000 7 0x2aa 0x3ff (x + 7) % 2 10 0x3d1 0x326 up4[15:6] 0x000 8 0x155 0x000 (x + 8) % 2 10 0x18e 0x10f up1[15:6] 0x000 9 0x2aa 0x3ff (x + 9) % 2 10 0x2cb 0x3fd up2[15:6] 0x000 10 0x155 0x000 (x + 10) % 2 10 0x0f1 0x31e up3[15:6] 0x000 11 0x2aa 0x3ff (x + 11) % 2 10 0x3dd 0x008 up4[15:6] 0x000 table 33 . scrambler 8 - bit input (register 0x573[5:4] = 'b10) 8 - bit octet number alternating checkerboard 1/0 word toggle ramp pn9 pn23 user repeat user single 0 0x55 0x00 (x) % 2 8 0x49 0xff up1[15:9] up1[15:9] 1 0xaa 0xff (x + 1) % 2 8 0x6f 0x5c up2[15:9] up2[15:9] 2 0x55 0x00 (x + 2) % 2 8 0xc9 0x00 up3[15:9] up3[15:9] 3 0xaa 0xff (x + 3) % 2 8 0xa9 0x29 up4[15:9] up4[15:9] 4 0x55 0x00 (x + 4) % 2 8 0x98 0xb8 up1[15:9] 0x00 5 0xaa 0xff (x + 5) % 2 8 0x0c 0x0a up2[15:9] 0x00 6 0x55 0x00 (x + 6) % 2 8 0x65 0x3d up3[15:9] 0x00 7 0xaa 0xff (x + 7) % 2 8 0x1a 0x72 up4[15:9] 0x00 8 0x55 0x00 (x + 8) % 2 8 0x5f 0x9b up1[15:9] 0x00 9 0xaa 0xff (x + 9) % 2 8 0xd1 0x26 up2[15:9] 0x00 10 0x55 0x00 (x + 10) % 2 8 0x63 0x43 up3[15:9] 0x00 11 0xaa 0xff (x + 11) % 2 8 0xac 0xff up4[15:9] 0x00 data link layer test modes the data link layer test modes are implemented in the ad9680 as defined by section 5.3.3.8.2 in the jedec jesd204b specification. these tests are shown in register 0x574 bits[2:0]. test patterns inserted at this point are useful for verifying the funct ionality of the data link layer. when the data link layer test modes are enabled, disable syncinb by writing 0xc0 to register 0x572.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 81 of 97 serial port interfac e the ad9680 spi allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on th e application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the memory map section. for detailed operational information , see the serial control interface standard (rev. 1.0) . configu ration using the spi three pins define the spi of the ad9680 adc: the sclk pin, the sdio pin, and the csb pin (see table 34 ). the sclk (serial clock) pin is used to synchronize the read and write data presented from/to the adc. the sdio (serial data input/output) pin is a dual - purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active low control that enables or disables the read and write cycles. table 34 . serial port interface pins pi n function sclk serial clock. the serial shift clock input that is used to synchronize serial interface , reads, and writes. sdio serial data input/output. a dual - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of csb, in conjunction with the rising edge of sclk, determines the start of the framing. an examp le of the serial timing and its definitions can be found in figure 4 and table 5 . other modes involving the csb pin are available. the csb pin can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow additional external timing. when csb is tied high , spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued, which al lows the sdio pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a readback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the serial control interface standard (rev. 1.0) . hardware interface the pins described in table 34 comprise the physical interface between the user programming devi ce and the serial port of the ad9680 . the sc lk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and a s an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note, microcontroller - based serial port interface (spi) boot circuit . do not activate t he spi port during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signa l are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9680 to prevent these signals from transitioning at the converter inputs during critical sampling periods. spi accessible featu res table 35 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the serial control interface standard (rev. 1.0) . the ad9680 device - specific features are described in the memory map section. table 35 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode. clock allows the user to access the clock divider via the spi. ddc allows the user to set up decimation filters for different applications. test input/output allows the user to set test modes to have known data on output bits. output mode allows the user to set up outputs. serdes output setup allows the user to vary serdes settings such as swing and emphasis.
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 82 of 97 memory map reading the memory m ap register table each row in the memory map register table has eight bit locations. the memory map is divided into four sections: the analog devices spi registers (register 0x000 to register 0x00d), the analog input buffer control registers, the adc function registers, the ddc function registers, and the digital outputs and test modes registers. tabl e 36 (see the memory map register table section) documents the default hexadecimal value for each h exadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x561, the output mode register, has a hexadecimal default value of 0x01, which means that bit 0 = 1, and the remain ing bits are 0s. this setting is the default output format value, which is twos complement. for more information on this function and others, see table 36. open and reserved locations all address and bit locations that are not included in table 36 are not currently supported for this device. write unused bits of a valid address location with 0s unless the default value is set otherwise. writing to these locations is required only when part of an address location is unassigned (for example, address 0x561). if the entire address location is open (for example, address 0x13), do not write to this address location. default values after the ad9680 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 36. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. ? x denotes a dont care bit. channel - specific registers some channel setup functions, such as the input termination (register 0x016), can be programmed to a different value for each channel. in these cases, channel address locations are internally duplicated for eac h channel. these registers and bits are designated in table 36 as local. these local registers and bits can be accessed by setting the appropriate c hannel a or channel b bits in register 0x008. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, set only channel a or channel b to read one of the two registers. if both bits are set during an spi read cycl e, the device returns the value for channel a. registers and bits designated as global in table 36 affect the entire device and the channel features f or which independent settings are not allowed between channels. the settings in register 0x005 do not affect the global registers and bits. spi soft reset after issuing a soft reset by programming 0x81 to register 0x000 , the ad9680 requires 5 ms to recover. when programming the ad9680 for application setup, ensure that an adequate delay is programmed into the f irmware after asserting the soft reset and before starting the device setup.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 83 of 97 memory map register table all address locations that are not included in table 36 are not currently supported for this device and should not be written. table 36 . memory map registers reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes analog devices spi registers 0x000 interface_ config_a soft reset (self clearing) lsb f irst 0 = msb 1 = lsb address ascension 0 0 address ascension lsb f irst 0 = msb 1 = lsb soft reset (self clearing) 0x00 0x001 interface_ config_b single instruction 0 0 0 0 0 datapath soft reset (self clearing) 0 0x00 0x002 device_ config (local) 0 0 0 0 0 0 00 = normal operation 10 = standby 11 = power - down 0x00 0x003 chip_type 011 = high speed adc 0x03 read only 0x004 chip_id (low byte) 1 1 0 0 0 1 0 1 0xc5 read only 0x005 chip_id (high byte) 0 0 0 0 0 0 0 0 0x00 read only 0x006 chip_ grade 1100 = 1250 msps 1010 = 1000 msps 1000 = 820 msps 0101 = 500 msps x x x x read only 0x008 device index 0 0 0 0 0 0 channel b channel a 0x0 0x00a scratch pad 0 0 0 0 0 0 0 0 0x00 0x00b spi revision 0 0 0 0 0 0 0 1 0x01 0x00c vendor id (low byte) 0 1 0 1 0 1 1 0 0x56 read only 0x00d vendor id (high byte) 0 0 0 0 0 1 0 0 0x04 read only analog input buffer control registers 0x015 analog input (local) 0 0 0 0 0 0 0 input disable 0 = normal operation 1 = input disabled 0x00 0x016 input termination (local) analog input differential termination 0000 = 400 ? (default) 0001 = 200 ? 0010 = 100 ? 0110 = 50 ? 1110 = ad9680 - 1250 and ad9680 - 1000 1100 = ad9680 - 820 and ad9680 - 500 0x0e for ad9680 - 1250 and ad9680 - 1000 ; 0x0c for ad9680 - 820 and ad9680 - 500 0x934 input capacitance (local) 0 0 0 0x1f = 3 pf to gnd (default) 0x00 = 1.5 pf to gnd 0x1f
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 84 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x018 buffer control 1 (local) 0000 = 1.0 buffer current 0001 = 1.5 buffer current 0010 = 2.0 buffer current (default for ad9680 - 500 ) 0011 = 2.5 buffer current 0100 = 3.0 buffer current (default for ad9680 - 1000 and ad9680 - 820 ) 0101 = 3.5 buffer current (default for ad9680 - 1250) 1111 = 8.5 buffer current 0 0 0 0 0x50 for ad9680 - 1250 ; 0x40 for ad9680 - 1000 and ad9680 - 820 ; 0x20 for ad9680 - 500 0x019 buffer control 2 (local) 0100 = setting 1 (default for ad9680 - 820 ) 0101 = setting 2 (default for ad9680 - 1250 and ad9680 - 1000 ) 0110 = setting 3 (default for ad9680 - 500 ) 0111 = setting 4 0 0 0 0 0x50 for ad9680 - 1250 and ad9680 - 1000 ; 0x40 for ad9680 - 820 ; 0x60 for ad9680 - 500 0x01a buffer control 3 (local) 0 0 0 0 1000 = setting 1 1001 = setting 2 (default for ad9680 - 1250 , ad9680 - 1000 and ad9680 - 820 ) 1010 = setting 3 (default for ad9680 - 500 ) 0x09 for ad9680 - 1250 , ad9680 - 1000 and ad9680 - 820 ; 0x0a for ad9680 - 500 0x11a buffer control 4 (local) 0 0 high frequency setting 0 = off (default) 1 = on 0 0 0 0 0 0x935 buffer control 5 (local) 0 0 0 0 0 low frequency operation 0 = off 1 = on (default) 0 0 0x025 input full - scale range (local) 0 0 0 0 full - scale adjust 0000 = 1.94 v 1000 = 1.46 v 1001 = 1.58 v (default for ad9680 - 1250 ) 1010 = 1.70 v (default for ad9680 - 1000 and ad9680 - 820 ) 1011 = 1.82 v 1100 = 2.06 v (default for ad9680 - 50 0 ) 0x09 for ad9680 - 1250 ; 0x0a for ad9680 - 1000 and ad9680 - 820 ; 0x0c for ad9680 - 500 v p - p differ - ential; use in conjunc - tion with reg. 0x030 0x030 input full - scale control (local) 0 0 0 full - scale control see table 10 for recommended settings for different frequency bands; default values: ad9680 - 1250 , ad9680 - 1000 = 110 ad9680 - 820 = 101 ad9680 - 500 = 001 ad9680 - 500 = 110 (for <1.82 v) 0 0 used in conjunc - tion with reg. 0x025
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 85 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes adc function registers 0x024 v_1p0 control 0 0 0 0 0 0 0 1.0 v reference select 0 = internal 1 = external 0x00 0x028 temperature diode 0 0 0 0 0 0 0 diode selection 0 = no diode selected 1 = temper - ature diode selected 0x00 used in conjunc - tion with reg. 0x040 0x03f pdwn/ stby pin control (local) 0 = pdwn/ stby enabled 1 = disabled 0 0 0 0 0 0 0 0x00 used in conjunc - tion with reg. 0x040 0x040 chip pin control pdwn/stby function 00 = power down 01 = standby 10 = disabled fast detect b (fd_b) 000 = fast detect b output 001 = jesd204b lmfc output 010 = jesd204b internal sync~ output 111 = disabled fast detect a (fd_a) 000 = fast detect a output 001 = jesd204b lmfc output 010 = jesd204b internal sync~ output 011 = temperature diode 111 = disabled 0x3f 0x10b clock divider 0 0 0 0 0 000 = divide by 1 001 = divide by 2 011 = divide by 4 111 = divide by 8 0x00 0x10c clock divider phase (local) 0 0 0 0 independently controls channel a and channel b clock divider phase offset 0000 = 0 input clock cycles delayed 0001 = ? input clock cycles delayed 0010 = 1 input clock cycles delayed 0011 = 1? input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2? input clock cycles delayed 1111 = 7? input clock cycles delayed 0x00 0x10d clock divider and sysref control clock divider auto phase adjust 0 = disabled 1 = enabled 0 0 0 clock divider negative skew window 00 = no negative skew 01 = 1 device clock of negative skew 10 = 2 device clocks of negative skew 11 = 3 device clocks of negative skew clock divider positive skew window 00 = no positive skew 01 = 1 device clock of positive skew 10 = 2 device clocks of positive skew 11 = 3 device clo cks of positive skew 0x00 clock divider must be >1 0x117 clock delay control 0 0 0 0 0 0 0 clock fine delay adjust enable 0 = disabled 1 = enabled 0x00 enabling the clock fine delay adjust causes a datapath reset
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 86 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x118 clock fine delay (local) clock fine delay adjust [7:0], twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps ?88 = ?151.7 ps skew ?87 = ?150 ps skew 0 = 0 ps skew +87 = +150 ps skew 0x00 used in con - junction with reg. 0x0117 0x11c clock status 0 0 0 0 0 0 0 0 = no input clock detected 1 = input clock detected read only 0x120 sysref control 1 0 sysref flag reset 0 = normal o pera - tion 1 = flags held in reset 0 sysref transition select 0 = low to high 1 = high to low clk edge select 0 = rising 1 = falling sysref mode select 00 = disabled 01 = continuous 10 = n shot 0 0x00 0x121 sysref control 2 0 0 0 0 sysref n - shot ignore counter select 0000 = next sysref only 0001 = ignore the first sysref transition 0010 = ignore the first two sysref transitions 1111 = ignore the first 16 sysref transitions 0x00 mode select (reg 0x120, bits [2:1]) must be n - shot 0x123 sysref timestamp delay control sysref timestamp delay, bits[6:0] 0x00 = no delay 0x01 = 1 clock delay 0x7f = 127 clocks delay 0x00 ignored when reg. 0x01ff = 0x00 0x128 sysref status 1 sysref hold status, register 0x128[7:4], refer to table 28 sysref setup status, register 0x128[3:0], refer to table 28 read only 0x129 sysref and clock divider status 0 0 0 0 clock divider phase when sysref was captured 0000 = in - phase 0001 = sysref is ? cycle delayed from clock 0010 = sysref is 1 cycle delayed from clock 0011 = 1? input clock cycles delayed 0100 = 2 input clock cycles delayed 0101 = 2? input clock cycles delayed 1111 = 7? input clock cycles delayed read on ly 0x12a sysref counter sysref counter, bits[7:0] increments when a sysref is captured read only 0x1ff chip sync mode synchronization mode 00 = normal 01 = timestamp 0x00 0x200 chip application mode 0 0 chip q ignore 0 = normal (i/q) 1 = ignore (i only) 0 0 0 chip operating mode 00 = full bandwidth mode 01 = ddc 0 on 10 = ddc 0 and ddc 1 on 11 = ddc 0, ddc 1, ddc 2, and ddc 3 on 0x00 0x201 chip decimation ratio 0 0 0 0 0 chip decimation ratio select 000 = full sample rate (decimate = 1) 001 = decimate by 2 010 = decimate by 4 011 = decimate by 8 100 = decimate by 16 0x00 0x228 customer offset offset adjust in lsbs from +127 to ?128 (twos complement format) 0x00
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 87 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x245 fast detect (fd) control (local) 0 0 0 0 force fd_a/ fd_b pins; 0 = normal function; 1 = force to value force value of fd_a/fd_b pins if force pins is true, this value is output on fd pins 0 enable fast detect output 0x00 0x247 fd upper threshold lsb (local) fast detect upper threshold, bits[7:0] 0x00 0x248 fd upper threshold msb (local) 0 0 0 fast detect upper threshold, bits[12:8] 0x00 0x249 fd lower threshold lsb (local) fast detect lower threshold, bits[7:0] 0x00 0x24a fd lower threshold msb (local) 0 0 0 fast detect lower threshold, bits[12:8] 0x00 0x24b fd dwell time lsb (local) fast detect dwell time, bits[7:0] 0x00 0x24c fd dwell time msb (local) fast detect dwell time, bits[15:8] 0x00 0x26f signal monitor synchroniza - tion control 0 0 0 0 0 0 synchronization mode 00 = disabled 01 = continuous 1 1 = one shot 0x00 refer to the signal monitor section 0x270 signal monitor control (local) 0 0 0 0 0 0 peak detector 0 = disabled 1 = enabled 0 0x00 0x271 signal monitor period register 0 (local) signal monitor period, bits[7:0] 0x80 in deci - mated output clock cycles 0x272 signal monitor period register 1 (local) signal monitor period, bits[15:8] 0x00 in deci - mated output clock cycles 0x273 signal monitor period register 2 (local) signal monitor period, bits[23:16] 0x00 in deci - mated output clock cycles 0x274 signal monitor result control (local) 0 0 0 result update 1 = update results (self clear) 0 0 0 result selection 0 = reserved 1 = peak detector 0x01 0x275 signal monitor result register 0 (local) signal monitor result, bits[7:0] when register 0x0274[0] = 1, result bits [19:7] = peak detector absolute value [12:0]; result bits [6:0] = 0 read only updated based on reg. 0x274[4]
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 88 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x276 signal monitor result register 1 (local) signal monitor result, bits[15:8] read only updated based on reg. 0x274[4] 0x277 signal monitor result register 1 (local) 0 0 0 0 signal monitor result, bits[19:16] read only updated based on reg. 0x274[4] 0x278 signal monitor period counter result (local) period count result, bits[7:0] read only updated based on reg. 0x274[4] 0x279 signal monitor sport over jesd204b control (local) 0 0 0 0 0 0 00 = disabled 11 = enable 0x00 0x27a sport over jesd204b input selection (local) 0 0 0 0 0 0 peak detector 0 = disabled 1 = enabled 0 0x00 ddc function registers (see the digital downconverter (ddc) section) 0x300 ddc synchro - nization control 0 0 0 ddc nco soft reset 0 = normal operation 1 = reset 0 0 synchronization mode (triggered by sysref ) 00 = disabled 01 = continuous 1 1 = one shot 0x310 ddc 0 control mixer select 0 = real mixer 1 = complex mixer gain select 0 = 0 db gain 1 = 6 db gain if (intermediate frequency) mode 00 = variable if mode (mixers and nco enabled) 01 = 0 hz if mode (mixer bypassed, nco disabled) 10 = f s /4 hz if mode (f s /4 down mixing mode) 11 = test mode (mixer inputs forced to +f s , nco enabled) complex to real enable 0 = disabled 1 = enabled 0 decimation ra te select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 0x311 ddc 0 input selection 0 0 0 0 0 q input select 0 = ch a 1 = ch b 0 i input select 0 = ch a 1 = ch b 0x00 refer to the ddc section 0x314 ddc 0 frequency lsb ddc 0 nco frequency value, bits[7:0] twos complement 0x00 0x315 ddc 0 frequency msb x x x x ddc 0 nco frequency value, bits[11:8] twos complement 0x00 0x320 ddc 0 phase lsb ddc 0 nco phase value, bits[7:0] twos complement 0x00 0x321 ddc 0 phase msb x x x x ddc 0 nco phase value, bits[11:8] twos complement 0x00
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 89 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x327 ddc 0 output test mode selection 0 0 0 0 0 q output test mode enable 0 = disabled 1 = enabled from channel b 0 i output test mode enable 0 = disabled 1 = enabled from channel a 0x00 refer to the ddc section 0x330 ddc 1 control mixer select 0 = real mixer 1 = complex mixer gain select 0 = 0 db gain 1 = 6 db gain if (intermediate frequency) mode 00 = variable if mode (mixers and nco enabled) 01 = 0 hz if mode (mixer bypassed, nco disabled) 10 = f adc /4 hz if mode (f adc /4 downmixing mode) 11 = test mode (mixer inputs forced to +f s , nco enabled) complex to re al enable 0 = disabled 1 = enabled 0 decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = deci mate by 8 0x00 0x331 ddc 1 input selection 0 0 0 0 0 q input select 0 = ch a 1 = ch b 0 i input select 0 = ch a 1 = ch b 0x05 refer to the ddc section 0x334 ddc 1 frequency lsb ddc 1 nco frequency value, bits[7:0] twos complement 0x00 0x335 ddc 1 frequency msb x x x x ddc 1 nco frequency value, bits[11:8] twos complement 0x00 0x340 ddc 1 phase lsb ddc 1 nco phase value, bits[7:0] twos complement 0x00 0x341 ddc 1 phase msb x x x x ddc 1 nco phase value, bits[11:8] twos complement 0x00 0x347 ddc 1 output test mode selection 0 0 0 0 0 q output test mode enable 0 = disabled 1 = enabled from ch b 0 i output test mode enable 0 = disabled 1 = enabled from ch a 0x00 refer to the ddc section 0x350 ddc 2 control mixer select 0 = real mixer 1 = complex mixer gain select 0 = 0 db gain 1 = 6 db gain if mode 00 = variable if mode (mixers and nco enabled) 01 = 0 hz if mode (mixer bypassed, nco disabled) 10 = f adc /4 hz if mode (f adc /4 down mixing mode) 11 = test mode (mixer inputs forced to +f s , nco enabled) complex to real enable 0 = disabled 1 = enabled 0 decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = d ecimate by 4 10 = decimate by 8 0x00 0x351 ddc 2 input selection 0 0 0 0 0 q input select 0 = ch a 1 = ch b 0 i input select 0 = ch a 1 = ch b 0x00 refer to the ddc section 0x354 ddc 2 frequency lsb ddc 2 nco frequency value, bits[7:0] twos complement 0x00
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 90 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x355 ddc2 frequency msb x x x x ddc 2 nco frequency value, bits[11:8] twos complement 0x00 0x360 ddc 2 phase lsb ddc 2 nco phase value, bits[7:0] twos complement 0x00 0x361 ddc 2 phase msb x x x x ddc 2 nco phase value, bits[11:8] twos complement 0x00 0x367 ddc 2 output test mode selection 0 0 0 0 0 q output test mode enable 0 = disabled 1 = enabled from ch b 0 i output test mode enable 0 = disabled 1 = enabled from ch a 0x00 refer to the ddc section 0x370 ddc 3 control mixer select 0 = real mixer 1 = complex mixer gain select 0 = 0 db gain 1 = 6 db gain if mode 00 = variable if mode (mixers and nco enabled) 01 = 0 hz if mode(mixer bypassed, nco disabled) 10 = f adc /4 hz if mode (f adc /4 downmixing mode) 11 = test mode (mixer inputs forced to +f s , nco enabled) complex to real enable 0 = disabled 1 = enabled 0 decimation rate select (complex to real disabled) 11 = decimate by 2 00 = decimate by 4 01 = decimate by 8 10 = decimate by 16 (complex to real enabled) 11 = decimate by 1 00 = decimate by 2 01 = decimate by 4 10 = decimate by 8 0x00 0x371 ddc 3 input selection 0 0 0 0 0 q input select 0 = ch a 1 = ch b 0 i input select 0 = ch a 1 = ch b 0x05 refer to the ddc section 0x374 ddc 3 frequency lsb ddc 3 nco frequency value, bits[7:0] twos complement 0x00 0x375 ddc 3 frequency msb x x x x ddc 3 nco frequency value, bits[11:8] twos complement 0x00 0x380 ddc3 phase lsb ddc 3 nco phase value, bits[7:0] twos complement 0x00 0x381 ddc 3 phase msb x x x x ddc 3 nco phase value, bits[11:8] twos complement 0x00 0x387 ddc 3 output test mode selection 0 0 0 0 0 0 0 i output test mode enable 0 = disabled 1 = enabled from ch a 0x00 refer to the ddc section digital outputs and test modes 0x550 adc test modes (local) user pattern selection 0 = cont i - nuous repeat 1 = single pattern 0 reset pn long gen 0 = long pn enable 1 = long pn reset reset pn short gen 0 = short pn enable 1 = short pn reset test mode selection 0000 = off, normal operation 0001 = midscale short 0010 = positive full scale 0011 = negative full scale 0100 = alternating checker board 0101 = pn sequence, long 0110 = pn sequence, short 0111 = 1/0 word toggle 1000 = the user pattern test mode (used with register 0x0550, bit 7 and user pattern 1 to user pa ttern 4 registers) 1111 = ramp output 0x00
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 91 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x551 user pattern 1 lsb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x552 user pattern 1 msb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x553 user pattern 2 lsb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x554 user pattern 2 msb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x555 user pattern 3 lsb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x556 user pattern 3 msb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x557 user pattern 4 lsb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x558 user pattern 4 msb 0 0 0 0 0 0 0 0 0x00 used with reg. 0x550 and reg. 0x573 0x559 output mode control 1 0 converter control bit 1 selection 000 = tie low (1b0) 001 = overrange bit 011 = fast detect (fd) bit 101 = sysref only used when cs (register 0x58f) = 2 or 3 0 converter control bit 0 selection 000 = tie low (1b0) 001 = overrange bit 011 = fast detect (fd) bit 101 = sysref on ly used when cs (register 0x58f) = 3 0x00 0x55a output mode control 2 0 0 0 0 0 converter control bit 2 selection 000 = tie low (1b0) 001 = overrange bit 011 = fast detect (fd) bit 101 = sysref used when cs (register 0x58f) = 1, 2, or 3 0x01 0x561 output mode 0 0 0 0 0 sample invert 0 = normal 1 = sample invert data format select 00 = offset binary 01 = twos complement 0x01 0x562 output overrange (or) clear virtual converter 7 or 0 = or bit enabled 1 = or bit cleared virtual converter 6 or 0 = or bit enabled 1 = or bit cleared virtual converter 5 or 0 = or bit enabled 1 = or bit cleared virtual converter 4 or 0 = or bit enabled 1 = or bit cleared virtual converter 3 or 0 = or bit enabled 1 = or bit cleared virtual converter 2 or 0 = or bit enabled 1 = or bit cleared virtual converter 1 or 0 = or bit enabled 1 = or bit cleared virtual converter 0 or 0 = or bit enabled 1 = or bit cleared 0x00
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 92 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x563 output or status virtual converter 7 or 0 = no or 1 = or occurred virtual convert er 6 or 0 = no or 1 = or occurred virtual converter 5 or 0 = no or 1 = or occurred virtual converter 4 or 0 = no or 1 = or occurred virtual converter 3 or 0 = no or 1 = or occurred virtual converter 2 or 0 = no or 1 = or occurred virtual converter 1 or 0 = no or 1 = or occurre d virtual converter 0 or 0 = no or 1 = or occurred 0x00 read only 0x564 output channel select 0 0 0 0 0 0 0 converter channel swap 0 = normal channel ordering 1 = channel swap enabled 0x00 0x56e jesd204b lane rate control 0 0 0 0 = serial lane rate 6.25 gbps and 12.5 gbps 1 = serial lane rate must be 3.125 gbps and 6.25 gbps 0 0 0 0 0x00 for ad9680 - 1250 , ad9680 - 1000 and ad9680 - 820 ; 0x10 for ad9680 - 500 0x56f jesd204b pll lock status pll lock 0 = not locked 1 = locked 0 0 0 0 0 0 0 0x00 read only 0x570 jesd204b quick config - uration jesd204b quick configuration l = number of lanes = 2 register 0x570, bits[7:6] m = number of converters = 2 register 0x570, bits[5:3] f = number of octets/frame = 2 register 0x570, bits[2:0] 0x88 for ad9680 - 1250 , ad9680 - 1000 and ad9680 - 820 ; 0x49 for ad9680 - 500 refer to table 26 and table 27 0x571 jesd204b link mode control 1 standby mode 0 = all converter outputs 0 1 = cgs (/k28.5/) tail bit (t) pn 0 = disable 1 = enable t = n ? ? n ? cs long transport layer test 0 = disable 1 = enable lane synch - ronization 0 = disable faci uses /k28.7/ 1 = enable faci uses /k28.3/ and /k28.7/ ilas sequence mode 00 = ilas disabled 01 = ilas enabled 11 = ilas always on test mode faci 0 = enabled 1 = disabled link control 0 = active 1 = power down 0x14 0x572 jesd204b link mode control 2 syncinb pin control 00 = normal 10 = ignore syncinb (force cgs) 11 = ignore syncinb (force ilas/user data) syncinb pin invert 0 = active low 1 = active high syncinb pin type 0 = differential 1 = cmos 0 8 - bit/10 - bit bypass 0 = normal 1 = bypass 8 - /10 - bit bit invert 0 = normal 1 = invert the abcd efghij symbols 0 0x00
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 93 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x573 jesd204b link mode control 3 chksum mode 00 = sum of all 8 - bit link config registers 01 = sum of individual link config fields 10 = checksum set to zero test injection point 00 = n? sample input 01 = 10 - bit data at 8 - bit/10 - bit output (for phy testing) 10 = 8 - bit data at scrambler input jesd204b test mode patterns 0000 = normal operation (test mode disabled) 0001 = alternating check er board 0010 = 1/0 word toggle 0011 = 31 - bit pn sequence x 31 + x 28 + 1 0100 = 23 - bit pn sequence x 23 + x 18 + 1 0101 = 15 - bit pn sequence x 15 + x 14 + 1 0110 = 9 - bit pn sequence x 9 + x 5 + 1 0111 = 7 - bit pn sequence x 7 + x 6 + 1 1000 = ramp output 1110 = continuous/repeat user test 1111 = single user test 0x00 0x574 jesd204b link mode control 4 ilas delay 0000 = transmit ilas on first lmfc after syncinb deasserted 0001 = transmit ilas on second lmfc after syncinb deasserted 1111 = transmit ilas on 16 th lmfc after syncinb deasserted 0 link layer test mode 000 = normal operation (link layer test mode disabled) 001 = continuous sequence of /d21.5/ characters 100 = modified rpat test sequence 101 = jspat test sequence 110 = jtspat test sequence 0x00 0x578 jesd204b lmfc offset 0 0 0 lmfc phase offset value[4:0] 0x00 0x580 jesd204b did config jesd204b tx did value[7:0] 0x00 0x581 jesd204b bid config 0 0 0 0 jesd204b tx bid value, bits[3:0] 0x00 0x583 jesd204b lid config 1 0 0 0 lane 0 lid value, bits[4:0] 0x00 0x584 jesd204b lid config 2 0 0 0 lane 1 lid value, bits[4:0] 0x01 0x585 jesd204b lid config 3 0 0 0 lane 2 lid value, bits[4:0] 0x01 0x586 jesd204b lid config 4 0 0 0 lane 3 lid value, bits[4:0] 0x03 0x58b jesd204b parameters scr/l jesd204b scrambling (scr) 0 = disabled 1 = enabled 0 0 0 0 0 jesd204b lanes (l) 00 = 1 lane 01 = 2 lanes 11 = 4 lanes read only, see register 0x570 0x8x 0x58c jesd204b f config number of octets per frame, f = register 0x58c[7:0] + 1 0x88 read only, see reg. 0x570 0x58d jesd204b k config 0 0 0 number of frames per multiframe, k = register 0x58d[4:0] + 1 only values where (f k) mod 4 = 0 are supported 0x1f see reg. 0x570 0x58e jesd204b m config number of converters p er link [7:0] 0x00 = link connected to one virtual converter (m = 1) 0x01 = link connected to two virtual converters (m = 2) 0x03 = link connected to four virtual converters (m = 4) 0x07 = link connected to eight virtual converters (m = 8) read only 0x58f jesd204b cs/n config number of control bits (cs) per sample 00 = no control bits (cs = 0) 01 = 1 control bit (cs = 1); control bit 2 only 10 = 2 control bits (cs = 2); control bit 2 and 1 only 11 = 3 control bits (cs = 3); all control bits (2, 1, 0) 0 adc converter resoluti on (n) 0x06 = 7 - bit resolution 0x07 = 8 - bit resolution 0x08 = 9 - bit resolution 0x09 = 10 - bit resolution 0x0a = 11 - bit resolution 0x0b = 12 - bit resolution 0x0c = 13 - bit resolution 0x0d = 14 - bit resolution 0x0e = 15 - bit resolution 0x0f = 16 - bit resolut ion 0x0f
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 94 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x590 jesd204b n config 0 0 subclass support (subclass v) 0 = subclass 0 (no deter - ministic latency) 1 = subclass 1 adc number of bits per sample (n) 0x7 = 8 bits 0xf = 16 bits 0x2f 0x591 jesd204b s config 0 0 1 samples per converter frame cycle (s) s value = register 0x591[4:0] + 1 0x20 read only 0x592 jesd204b hd and cf config hd value 0 = disabled 1 = enabled 0 0 control words per frame clock cycle per link (cf) cf value = register 0x592, bits[4:0] 0x80 read only 0x5a0 jesd204b chksum 0 chksum value for serdout0, bits[7:0] 0x81 read only 0x5a1 jesd204b chksum 1 chksum value for serdout1, bits[7:0] 0x82 read only 0x5a2 jesd204b chksum 2 chksum value for serdout2, bits[7:0] 0x82 read only 0x5a3 jesd204b chksum 3 chksum value for serdout3, bits[7:0] 0x84 read only 0x5b0 jesd204b lane power - down 1 serd - out3 0 = on 1 = off 1 serd - out2 0 = on 1 = off 1 serd - out1 0 = on 1 = off 1 serd - out0 0 = on 1 = off 0xaa 0x5b2 jesd204b lane serdout0 assign x x x x 0 serdout0 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x00 0x5b3 jesd204b lane serdout1 assign x x x x 0 serdout1 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x11 0x5b5 jesd204b lane serdout2 assign x x x x 0 serdout2 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x22 0x5b6 jesd204b lane serdout3 assign x x x x 0 serdout3 lane assignment 000 = logical lane 0 001 = logical lane 1 010 = logical lane 2 011 = logical lane 3 0x33 0x5bf jesd serializer drive adjust 0 0 0 0 swing voltage 0000 = 237.5 mv 0001 = 250 mv 0010 = 262.5 mv 0011 = 275 mv 0100 = 287.5 mv 0101 = 300 mv (default) 0110 = 312.5 mv 0111 = 325 mv 1000 = 337.5 mv 1001 = 350 mv 1010 = 362.5 mv 1011 = 375 mv 1100 = 387.5 mv 1101 = 400 mv 1110 = 412.5 mv 1111 = 425 mv 0x05
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 95 of 97 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x5c1 de - emphasis select 0 serd - out3 0 = disable 1 = enable 0 serd - out2 0 = disable 1 = enable 0 serdout1 0 = disable 1 = enable 0 serd - out0 0 = disable 1 = enable 0x00 0x5c2 de - emphasis setting for serdout0 0 0 0 0 serdout0 de - emphasis settings 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 0x5c3 de - emphasis setting for serdout1 0 0 0 0 serdout1 de - emphasis settings 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 0x5c4 de - emphasis setting for serdout2 0 0 0 0 serdout2 de - emphasis settings 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00 0x5c5 de - emphasis setting for serdout3 0 0 0 0 serdout3 de - emphasis settings 0000 = 0 db 0001 = 0.3 db 0010 = 0.8 db 0011 = 1.4 db 0100 = 2.2 db 0101 = 3.0 db 0110 = 4.0 db 0111 = 5.0 db 0x00
p r o duc t o v er vi e w o nline d o cume n t a tion design resou r c es d iscussion s ample & buy ad9680 data sheet rev. c | page 96 of 97 applications informa tion power supply recomme ndations the ad9680 must be powered by the following seven supplies: avdd1 = 1.25 v, avdd2 = 2.5 v, avdd3 = 3.3 v, avdd1_sr = 1.25 v, dvdd = 1.25 v, drvdd = 1.25 v, and spivdd = 1.80 v. for applications requirin g an optimal high power efficiency and low noise performance, it is recommended that the adp2164 and adp2370 switching regulators be u sed to convert the 3.3 v, 5.0 v, or 12 v input rails to an intermediate rail (1.8 v and 3.8 v). these intermediate rails are then postregulated by very low noise, low dropout (ldo) regulators ( ad p1741 , adm7172 , and adp125 ). figure 174 shows the recommended power supply scheme for the ad9680 . a vdd1 1.25v a vdd1_sr 1.25v dvdd 1.25v spivdd (1.8v or 3.3v) 3.6v 3.3v dr vdd 1.25v 1.8v 1 1752-063 adp1741 adp125 a vdd3 3.3v adm7172 or adp1741 a vdd2 2.5v adp1741 figure 174 . high efficiency, low noise power s olution for the ad9680 it is not necessary to split all of these power domains in all cases. the recommended solution shown in figure 174 provides the lowest noise, highest efficiency power delivery system for the ad9680 . if only one 1.25 v supply is available, route to avdd1 first and then tap it off and isolate it with a ferrite bead or a filter choke, preceded by decoupling capacitors for avdd1_sr, dvdd , and drvdd, in that order. this is shown as the optional path in figure 174 . the user can employ several different decoupling capacitors to cover both high and low frequencies. these capacitors must be located close to the point of entry at the pcb level and close to the devices, with minimal trace lengths. exposed pad thermal heat slug recommendations the exposed pad on the underside of the adc must be connected to agnd to achieve the best elec trical and thermal performance of the ad9680 . connect an exposed continuous copper plane on the pcb to the ad9680 exposed pad, pin 0. th e copper plane must have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias must be solder filled or plugged. the number of vias and the fill determine the resulting ja measured on the board. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the adc and pcb durin g the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. see figure 175 for a pcb layout example. for detailed inform ation on packaging and the pcb layout of chip scale packages, see the an - 772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) . 1 1752-064 figure 175 . recommended pcb layout of exposed pad for the ad9680 avdd1_sr (pin 57) an d agnd (pin 56 and p in 60) avdd1_sr (pin 57) and agnd (pin 56 and pin 60) can be used to provide a separ ate power supply node to the sysref circuits of ad9680 . if running in subclass 1, the ad9680 can support periodic one - shot or gapped si gnals. to minimize the coupling of this supply into the avdd1 supply node, adequate supply bypassing is needed.
p r o duc t o v er vi e w o nline do cume n ta tion design resou r c es d iscussion s ample & buy data sheet ad9680 rev. c | page 97 of 97 outline dimensions 0.50 bsc bot t om view top view pin 1 indic a t or exposed pa d pin 1 indic a t or 7.70 7.60 sq 7.50 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.18 02-12-2014- a 9.10 9.00 sq 8.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min 7.50 ref compliant to jedec standards mo-220-wmmd 1 64 16 17 49 48 32 33 pkg-004396 figure 176 . 64 - lead lead frame chip scale package [lfcsp_wq] 9 mm 9 mm body, very thin quad (cp - 64 - 15) dimensions shown in millimeters ordering guide model 1 temperature range package description 2 package option ad9680bcpz - 1250 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpz - 1000 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpz -820 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpz -500 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpzrl7 - 1250 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpzrl7 - 1000 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpzrl7 - 820 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680bcpzrl7 - 500 ?40c to +85c 64- lead lead frame chip scale package [lfcsp_wq] cp -64-15 ad9680 - 1250ebz evaluation board for ad9680 - 1250 ad9680 - 1000ebz evaluation board for ad9680 - 1000 ad9680 - lf1000ebz evaluation board for ad9680 - 1000 with 1 ghz bandwidth ad9680 - 820ebz evaluation board for ad9680 - 820 ad9680 - lf820ebz evaluation board for ad9680 - 820 with 1 ghz bandwidth ad9680 - 500ebz evaluation board for ad9680 - 500 ad9680 - lf500ebz evaluation board for ad9680 - 500 with 1 ghz bandwi d th 1 z = rohs compliant part. 2 t he ad9680 - 1250ebz , ad9680 - 1000ebz , ad9680 - 820eba , and ad9680 - 500ebz evaluation boards are optimized for full analog input frequency range of 2 ghz. ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11752 - 0- 11/15(c)

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